Patents by Inventor Gary B. Long

Gary B. Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160248210
    Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Sanka GANESAN, Timothy M. SWETTLEN, Gary B. LONG, Donald T. TRAN, Jill D. MURFIN, David I. AMIR
  • Patent number: 9332643
    Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sanka Ganesan, Timothy M. Swettlen, Gary B. Long, Donald T. Tran, Jill D. Murfin, David I. Amir
  • Publication number: 20140273552
    Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Sanka GANESAN, Timothy M. SWETTLEN, Gary B. LONG, Donald T. TRAN, Jill D. MURFIN, David D. AMIR
  • Patent number: 8307548
    Abstract: A method of making a printed circuit board panel, a printed circuit board panel made according to the method, and a system incorporating a printed circuit board provided onto the panel. The printed circuit board panel has a panel top edge, a panel bottom edge parallel to the panel top edge, and two parallel panel side edges, and further includes a first set of fiber bundles extending at the predetermined angle with respect to the panel side edges, and a second set of fiber bundles extending at the predetermined angle with respect to the panel top edge.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: November 13, 2012
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Bryce D. Horine
  • Publication number: 20100328919
    Abstract: A method of making a printed circuit board panel, a printed circuit board panel made according to the method, and a system incorporating a printed circuit board provided onto the panel. The printed circuit board panel has a panel top edge, a panel bottom edge parallel to the panel top edge, and two parallel panel side edges, and further includes a first set of fiber bundles extending at the predetermined angle with respect to the panel side edges, and a second set of fiber bundles extending at the predetermined angle with respect to the panel top edge.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Bryce D. Horine
  • Patent number: 7843057
    Abstract: A method of making a printed circuit board panel, a printed circuit board panel made according to the method, and a system incorporating a printed circuit board provided onto the panel. The printed circuit board panel has a panel top edge, a panel bottom edge parallel to the panel top edge, and two parallel panel side edges, and further includes a first set of fiber bundles extending at the predetermined angle with respect to the panel side edges, and a second set of fiber bundles extending at the predetermined angle with respect to the panel top edge.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Bryce D. Horine
  • Patent number: 7630601
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
  • Publication number: 20080159689
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Application
    Filed: February 26, 2008
    Publication date: July 3, 2008
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
  • Patent number: 7373068
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PUB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long, Michael W. Beckman
  • Patent number: 7361842
    Abstract: A method, apparatus, and system for a printed circuit board (PCB) and package with an embedded air dielectric includes a conductor formed on a surface of a first core layer, a conductor layer overlaying an inner surface of a cavity formed in a second core layer, the conductor layer opposing the conductor, and a sealed air channel between and separating the conductor and the conductor layer from contacting each other. A gas in the sealed air channel provides a primary dielectric therein. The gas may be air.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, William O. Alger, Gary B. Long, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7343576
    Abstract: A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. The first plurality of yarns are separated by a first weave pitch and the second plurality of yarns separated by a second weave pitch. At least two conductor traces are formed on the dielectric medium. The conductor traces are positioned on the dielectric medium such that the conductor traces each have substantially similar effective dielectric constants.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, William O. Alger, Carlos Mejia, Bryce Horine
  • Patent number: 7234947
    Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7145243
    Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multi-layered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
  • Patent number: 7121841
    Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7064063
    Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multilayered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
  • Patent number: 7043706
    Abstract: A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. The first plurality of yarns are separated by a first weave pitch and the second plurality of yarns separated by a second weave pitch. At least two conductor traces are formed on the dielectric medium. The conductor traces are positioned on the dielectric medium such that the conductor traces each have substantially similar effective dielectric constants.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, William O. Alger, Carlos Mejia, Bryce Horine
  • Patent number: 7022919
    Abstract: An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (Dk), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the Dk, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, William O. Alger, Dennis J. Miller
  • Patent number: 6916183
    Abstract: An apparatus for receiving a microchip and having a conductor buses therein. A top surface of the apparatus receives the microchip while the bottom surface is to mount to a circuit board. A plurality of pin receptacles pass through the top surface to receive a corresponding plurality of microchip pins of the microchip. The conductor bus resides at least in part between the top surface and the bottom surface and is electrically coupled to a first plurality of the plurality of the pin receptacles.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 12, 2005
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Carlos Mejia
  • Patent number: 6882762
    Abstract: A method is provided for forming a waveguide in a printed circuit board. This may include forming a trench in a printed circuit board substrate and forming at least one metalized surface along the trench. A metalized capping surface may be provided over the trench so as to form the waveguide structure.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Carlos Mejia, William O. Alger, Gary B. Long
  • Publication number: 20040262036
    Abstract: An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (Dk), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the Dk, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Gary A. Brist, Gary B. Long, William O. Alger, Dennis J. Miller