Patents by Inventor Gary Bronner
Gary Bronner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230012275Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.Type: ApplicationFiled: September 20, 2022Publication date: January 12, 2023Inventors: Zhichao LU, Brent HAUKNESS, Gary BRONNER
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Patent number: 11468947Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.Type: GrantFiled: December 21, 2020Date of Patent: October 11, 2022Assignee: Hefei Reliance Memory LimitedInventors: Zhichao Lu, Brent Haukness, Gary Bronner
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Publication number: 20210110870Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Zhichao LU, Brent HAUKNESS, Gary BRONNER
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Patent number: 10943655Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.Type: GrantFiled: August 22, 2017Date of Patent: March 9, 2021Assignee: Hefei Reliance Memory LimitedInventors: Zhichao Lu, Brent Haukness, Gary Bronner
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Publication number: 20190392897Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.Type: ApplicationFiled: August 22, 2017Publication date: December 26, 2019Inventors: Zhichao LU, Brent HAUKNESS, Gary BRONNER
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Patent number: 8583071Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.Type: GrantFiled: December 18, 2009Date of Patent: November 12, 2013Assignee: Rambus Inc.Inventors: Scott Best, Gary Bronner, Ely Tsern
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Publication number: 20110275356Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.Type: ApplicationFiled: December 18, 2009Publication date: November 10, 2011Applicant: Rambus Inc.Inventors: Scott Best, Gary Bronner, Ely Tsem
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Publication number: 20100025811Abstract: An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).Type: ApplicationFiled: November 29, 2007Publication date: February 4, 2010Inventors: Gary Bronner, Brent S. Haukness, Fariborz Assaderaghi, Mark D. Kellam, Mark Horowitz
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Publication number: 20080102569Abstract: A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.Type: ApplicationFiled: December 19, 2007Publication date: May 1, 2008Inventors: Kangguo Cheng, Gary Bronner, Ramachandra Divakaruni, Carl Radens
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Publication number: 20070249133Abstract: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.Type: ApplicationFiled: April 11, 2006Publication date: October 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary Bronner, David Fried, Jeffrey Gambino, Leland Chang, Ramachandra Divakaruni, Haizhou Yin, Gregory Costrini, Viraj Sardesai
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Publication number: 20060175660Abstract: A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Gary Bronner, Ramachandra Divakaruni, Carl Radens
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Publication number: 20060128111Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.Type: ApplicationFiled: February 10, 2006Publication date: June 15, 2006Applicant: International Business Machines CorporationInventors: Jochen Beintner, Gary Bronner, Ramachandra Divakaruni, Byeong Kim
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Publication number: 20060091442Abstract: The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.Type: ApplicationFiled: December 9, 2005Publication date: May 4, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Gary Bronner, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens
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Publication number: 20050277271Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.Type: ApplicationFiled: June 9, 2004Publication date: December 15, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jochen Beintner, Gary Bronner, Ramachandra Divakaruni, Byeong Kim
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Publication number: 20050247966Abstract: The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.Type: ApplicationFiled: May 6, 2004Publication date: November 10, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Gary Bronner, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens
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Publication number: 20050093044Abstract: In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Inventors: Kangguo Cheng, Ramachandra Divkaruni, Gary Bronner, Carl Radens, Oleg Gluschenkov
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Patent number: 6759291Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.Type: GrantFiled: January 14, 2002Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
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Patent number: 6656807Abstract: A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.Type: GrantFiled: January 30, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Gary Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David Horak, Jack A. Mandelman
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Patent number: 6614074Abstract: A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.Type: GrantFiled: June 5, 1998Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Gary Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David Horak, Jack A. Mandelman
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Patent number: 6548357Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: GrantFiled: April 8, 2002Date of Patent: April 15, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder