Patents by Inventor Gary Bronner
Gary Bronner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20030057483Abstract: A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.Type: ApplicationFiled: June 5, 1998Publication date: March 27, 2003Inventors: GARY BRONNER, TOSHIHARU FURUKAWA, MARK C. HAKEY, STEVEN J. HOLMES, DAVID HORAK, JACK A. MANDELMAN
-
Patent number: 6495876Abstract: A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.Type: GrantFiled: June 30, 2000Date of Patent: December 17, 2002Assignee: International Business Machines CorporationInventors: Gary Bronner, Ramachandra Divakaruni, Yoichi Takegawa
-
Publication number: 20020111025Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: ApplicationFiled: April 8, 2002Publication date: August 15, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
-
Patent number: 6426251Abstract: A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.Type: GrantFiled: June 28, 2001Date of Patent: July 30, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Gary Bronner, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
-
Publication number: 20020079528Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.Type: ApplicationFiled: January 14, 2002Publication date: June 27, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION AND INFINEON TECHNOLOGIES NORTH AMERICA CORPORATIONInventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
-
Patent number: 6403423Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: GrantFiled: November 15, 2000Date of Patent: June 11, 2002Assignee: International Business Machines CorporationInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
-
Patent number: 6388294Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.Type: GrantFiled: November 22, 2000Date of Patent: May 14, 2002Assignee: International Business Machines CorporationInventors: Carl Radens, Mary E. Weybright, Gary Bronner
-
Patent number: 6369419Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.Type: GrantFiled: June 23, 2000Date of Patent: April 9, 2002Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
-
Patent number: 6320215Abstract: A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.Type: GrantFiled: July 22, 1999Date of Patent: November 20, 2001Assignee: International Business Machines CorporationInventors: Gary Bronner, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
-
Publication number: 20010038113Abstract: A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.Type: ApplicationFiled: June 28, 2001Publication date: November 8, 2001Inventors: Gary Bronner, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
-
Publication number: 20010004540Abstract: A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.Type: ApplicationFiled: January 30, 2001Publication date: June 21, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David Horak, Jack A. Mandelman
-
Patent number: 6194301Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.Type: GrantFiled: July 12, 1999Date of Patent: February 27, 2001Assignee: International Business Machines CorporationInventors: Carl Radens, Mary E. Weybright, Gary Bronner
-
Patent number: 6174756Abstract: An efficient method of forming deep junction implants in one region without affecting the implant of a second region of an integrated circuit is provided. This is achieved by forming spacers of deep junction devices with the same material used to fill the gaps of shallow junction devices.Type: GrantFiled: September 30, 1997Date of Patent: January 16, 2001Assignee: Siemens AktiengesellschaftInventors: Jeffrey P. Gambino, Johann Alsmeier, Gary Bronner
-
Patent number: 6140208Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.Type: GrantFiled: February 5, 1999Date of Patent: October 31, 2000Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Farid Agahi, Gary Bronner, Bertrand Flietner, Erwin Hammerl, Herbert Ho, Radhika Srinivasan