Patents by Inventor Gary D. Hicok
Gary D. Hicok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9569279Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.Type: GrantFiled: December 21, 2012Date of Patent: February 14, 2017Assignee: NVIDIA CorporationInventors: Gary D. Hicok, Matthew Raymond Longnecker, Rahul Gautam Patel
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Publication number: 20150194128Abstract: One embodiment of the present invention sets forth a technique for generating a transparency effect for a computing device. The technique includes transmitting, to a camera, a synchronization signal associated with a refresh rate of a display. The technique further includes determining a line of sight of a user relative to the display, acquiring a first image based on the synchronization signal, and processing the first image based on the line of sight of the user to generate a first processed image. Finally, the technique includes compositing first visual information and the first processed image to generate a first composited image, and displaying the first composited image on the display.Type: ApplicationFiled: January 7, 2014Publication date: July 9, 2015Applicant: NVIDIA CORPORATIONInventor: Gary D. HICOK
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Publication number: 20140181501Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Gary D. Hicok, Matthew Raymond LONGNECKER, Rahul Gautam PATEL
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Patent number: 8635480Abstract: In a computer system with multiple processing units, power to one or more of the processing units is turned off while the other processing units remain powered on. The processing unit that is powered off may be a GPU on a graphics adapter card, and power to this GPU is controlled by turning on and off the power supplied through a voltage regulator. With this configuration, power to the GPU on the graphics adapter card can be turned off when it is not in use or when it is being used for graphics processing that another graphics processor can handle.Type: GrantFiled: February 26, 2008Date of Patent: January 21, 2014Assignee: Nvidia CorporationInventors: Ludger Mimberg, David G. Reed, David Wyatt, Gary D. Hicok, Rambod Jacoby
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Patent number: 8094670Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 3, 2007Date of Patent: January 10, 2012Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 8051126Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: October 29, 2009Date of Patent: November 1, 2011Assignee: NVIDIA CorporationInventors: Gary D. Hicok, Jr., Robert A. Alfieri
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Patent number: 7961733Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: June 18, 2008Date of Patent: June 14, 2011Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7924868Abstract: A novel network architecture that integrates the functions of an Internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 28, 2007Date of Patent: April 12, 2011Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Publication number: 20100049780Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Applicant: NVIDIA CorporationInventors: Gary D. Hicok, Robert A. Alfieri
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Patent number: 7620738Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: November 30, 2007Date of Patent: November 17, 2009Assignee: NVIDIA CorporationInventors: Gary D. Hicok, Robert A. Alfieri
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Publication number: 20080279188Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: ApplicationFiled: June 18, 2008Publication date: November 13, 2008Inventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7397797Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 13, 2002Date of Patent: July 8, 2008Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7383352Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: June 23, 2006Date of Patent: June 3, 2008Assignee: NVIDIA CorporationInventors: Gary D. Hicok, Robert A. Alfieri
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Publication number: 20080104271Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: ApplicationFiled: June 23, 2006Publication date: May 1, 2008Inventors: Gary D. Hicok, Robert A. Alfieri
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Patent number: 7362772Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 13, 2002Date of Patent: April 22, 2008Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7324547Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 13, 2002Date of Patent: January 29, 2008Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7289125Abstract: A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.Type: GrantFiled: February 27, 2004Date of Patent: October 30, 2007Assignee: NVIDIA CorporationInventors: Franck R. Diard, David G. Reed, Gary D. Hicok, Michael Brian Cox
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Patent number: 7188250Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.Type: GrantFiled: December 13, 2002Date of Patent: March 6, 2007Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
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Patent number: 7010724Abstract: Circuitry for detecting operating system hang conditions is provided. The circuitry includes interrupt logic for receiving system interrupts targeted for a central processing unit. Further included is hang detection logic that is in communication with the interrupt logic. The hang detection logic is capable of determining whether the central processing unit has processed an interrupt within a period of time. Hang resolution logic is further provided for removing the central processing unit from a hang state when it is determined that the interrupt has not been processed within the period of time.Type: GrantFiled: June 5, 2002Date of Patent: March 7, 2006Assignee: Nvidia CorporationInventor: Gary D. Hicok
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Patent number: 6848057Abstract: A novel method and apparatus for providing a decoupled power management state. The present invention decouples the operating system's perspective of the power management state from that of the actual hardware state of a host resource. Namely, the resources of a host computer can still operate and provide functionality while the host operating system is “off”, while still providing power saving to the host system and user.Type: GrantFiled: May 28, 2002Date of Patent: January 25, 2005Assignee: nVidia CorporationInventor: Gary D. Hicok