Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

Abstract: A novel method and apparatus for providing a decoupled power management state. The present invention decouples the operating system's perspective of the power management state from that of the actual hardware state of a host resource. Namely, the resources of a host computer can still operate and provide functionality while the host operating system is “off”, while still providing power saving to the host system and user.

Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

Abstract: A virtual memory manager for a multi-media engine allows individual media units to operate in their own virtual space in much the same way as a software program operating in virtual mode. The virtual memory controller performs address translation or mapping to the correct physical memory location (in local memory or system memory) and will also convert the data stream to or from a compressed format. In addition, the virtual memory controller provides a unified TLB (translation lookaside buffer) available to all media units. The TLB has four types of pointer entries which are controlled by two bits. The first bit controls whether the TLB entry is a direct map or a pointer to another translation table. the second bit controls whether the TLB entry is stored in a compressed format. The overall concept may allow dynamic load balancing between local media memory and system memory.

Abstract: An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity.

Abstract: A programmable filter is provided for filtering image or texture map data. A weighting RAM stores weighting data for filtering data in both x and y directions. Different weighting values may be programmed into weighting RAMs to provide different weighting functions and also enable or disable a number of taps within the filter. A weighting value of zero, for example, may disable a particular tap for the filter. In the preferred embodiment, a number of lines in the x direction may be simultaneously weighted and then weighted and combined in the y direction to produce a filtered value within one clock cycle.

Abstract: The present invention relates to a system and a method for reducing access times for retrieving audio samples. The system uses a wave table cache. The wave table cache allows devices such as a Digital Signal Processor (DSP) to retrieve audio samples in a linear fashion from the wave table cache at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system. The DSP may then use the audio samples to generate signals to create sounds based on the audio samples.

Abstract: A compositing buffer having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location. In a second embodiment of the present invention, the variable band size of the compositing buffer may allow for an external memory to be used for a compositing buffer, for example, a portion of the display memory (frame buffer). While such an embodiment may reduce overall bandwidth, the associated cost reduction may make such an apparatus appealing for low cost applications.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Abstract: The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is operatively connected to a plurality of storage mediums, a main memory and a central processing unit (CPU). The controller interface is preferably configured to receive and detect data transfer protocol requests having different timing parameters. Once the controller interface receives a data transfer protocol request, an arbitration unit that is operatively coupled to said controller interface assigns priorities to the detected data transfer protocols having different timing parameters. The arbitration unit then compares the assigned priorities, and interrupts an on-going data transfer protocol when a newly received data transfer protocol is assigned a higher priority. The data transfer protocol assigned the high priority is then commenced and proceeds to completion.

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device.

Abstract: A look ahead read buffer automatically senses the direction of the read sequence, sets the direction based on the current and previous read addresses, and prefetches data from memory to allow a Host device such as a CPU to read data out of the look ahead read buffer with no wait states, rather than accessing this data directly in slower memory that requires wait states. This read buffer is especially useful in applications such as display controllers that store and retrieve data in sequential format. The display memory may be partitioned into pages, and the read buffer will then determine and set the appropriate direction at page boundaries, and will not change direction within that page of display data. In addition, the read buffer inhibits reads that occur outside of the current page of display data, ignoring the effects of other reads that do not directly affect the display.

Abstract: A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.

Abstract: A hardware cursor is implemented on a typical video display controller, and uses an unused portion of video RAM as cursor memory to store the cursor information. Since the cursor memory may be located at any unused location of video RAM, it is a virtual hardware cursor since the location of cursor data may changed as required. The operation of the cursor may be programmed, monitored and controlled via control registers. The hardware cursor monitors the video control signals to determine when to put out cursor data rather than directly outputting pixel data. The hardware cursor fetches the appropriate cursor data from the cursor memory in the video RAM during the horizontal nondisplay period just prior to a line of display data that should contain cursor data. The hardware cursor then monitors the pixel stream and outputs unchanged pixel data until a cursor location is reached, at which time the hardware cursor outputs a logical combination of cursor data, cursor color, and pixel value.

Abstract: A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

Abstract: A method for selectively controlling the operation of a computer system so that the computer system is selectively caused to execute instructions of a first predetermined bit length or instructions of a second predetermined bit length. The method comprises the preliminary steps of storing instruction data in a set of EVEN instruction storage locations; storing instruction data in a set of ODD instruction locations; establishing an EVEN execution pointer; and establishing an ODD execution pointer. At a first given time, either the EVEN execution pointer is incremented by a predetermined COUNT or the ODD execution pointer is incremented by the predetermined COUNT; but both pointers are not simultaneously incremented by the COUNT. The method causes an instruction to be executed, which instruction was stored entirely in either an EVEN instruction location or entirely in an ODD instruction location.