Patents by Inventor Gary D. Polhemus
Gary D. Polhemus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10483193Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: January 15, 2019Date of Patent: November 19, 2019Assignee: Infineon Technologies Americas Corp.Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Publication number: 20190148272Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: ApplicationFiled: January 15, 2019Publication date: May 16, 2019Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 10224266Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: June 27, 2016Date of Patent: March 5, 2019Assignee: Infineon Technologies Americas Corp.Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 9831773Abstract: During operation, a protection circuit receives an input voltage representative of current delivered by a power supply phase to a load. In one configuration, the input voltage is received as the voltage across respective drain-source nodes of a synchronous switch (low side switch) disposed in a power supply. The protection circuit selectively controls conveyance of the input voltage so that damaging transient voltages on the input voltage are not passed to a downstream sampling circuit. The sampling circuit includes a capacitor circuit to store the sample of the input voltage. During operation, the sampling circuit utilizes the input voltage conveyed by the input voltage circuit to charge the capacitor with a sample voltage representative of the current.Type: GrantFiled: December 18, 2015Date of Patent: November 28, 2017Assignee: Infineon Technologies Americas Corp.Inventor: Gary D. Polhemus
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Publication number: 20170179824Abstract: During operation, a protection circuit receives an input voltage representative of current delivered by a power supply phase to a load. In one configuration, the input voltage is received as the voltage across respective drain-source nodes of a synchronous switch (low side switch) disposed in a power supply. The protection circuit selectively controls conveyance of the input voltage so that damaging transient voltages on the input voltage are not passed to a downstream sampling circuit. The sampling circuit includes a capacitor circuit to store the sample of the input voltage. During operation, the sampling circuit utilizes the input voltage conveyed by the input voltage circuit to charge the capacitor with a sample voltage representative of the current.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventor: Gary D. Polhemus
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Publication number: 20160307828Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 9390944Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: February 18, 2014Date of Patent: July 12, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 9171743Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: October 4, 2013Date of Patent: October 27, 2015Assignee: International Rectifier CorporationInventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Publication number: 20140162410Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: ApplicationFiled: February 18, 2014Publication date: June 12, 2014Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 8692360Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: July 6, 2010Date of Patent: April 8, 2014Assignee: International Rectifier CorporationInventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 8648449Abstract: According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.Type: GrantFiled: July 20, 2009Date of Patent: February 11, 2014Assignee: International Rectifier CorporationInventors: Gary D. Polhemus, Robert T. Carroll, Donald J. Desbiens
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Publication number: 20140030853Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: ApplicationFiled: October 4, 2013Publication date: January 30, 2014Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 8581343Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.Type: GrantFiled: July 6, 2010Date of Patent: November 12, 2013Assignee: International Rectifier CorporationInventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
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Patent number: 8022726Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.Type: GrantFiled: August 18, 2010Date of Patent: September 20, 2011Assignee: International Rectifier CorporationInventors: Anthony B. Candage, Gary D. Polhemus, Hrvoje Jasa, Robert T. Carroll
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Publication number: 20110018517Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.Type: ApplicationFiled: August 18, 2010Publication date: January 27, 2011Inventors: Anthony B. Candage, Gary D. Polhemus, Hrvoje Jasa, Robert T. Carroll
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Patent number: 7795915Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.Type: GrantFiled: August 4, 2008Date of Patent: September 14, 2010Assignee: CHiL Semiconductor CorporationInventors: Anthony B. Candage, Gary D. Polhemus, Hrvoje Jasa, Robert T. Carroll
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Publication number: 20100218003Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).Type: ApplicationFiled: June 16, 2006Publication date: August 26, 2010Applicant: AGERE SYSTEMS INC.Inventors: Matthew Blaha, Luis de La Torre, Alan L. Ellis, Gary D. Polhemus, Patrick J. Quirk
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Publication number: 20100187664Abstract: According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.Type: ApplicationFiled: July 20, 2009Publication date: July 29, 2010Inventors: Gary D. Polhemus, Robert T. Carroll, Donald J. Desbiens
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Publication number: 20100026261Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Inventors: Anthony B. Candage, Gary D. Polhemus, Hrvoje Jasa, Robert T. Carroll
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Patent number: 7656255Abstract: Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.Type: GrantFiled: February 28, 2007Date of Patent: February 2, 2010Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Robert J. Kapuschinsky, Gary D. Polhemus