Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.

Abstract: In some examples, a lock manager may receive a lock release message from a processor. The lock release message may identify a lock that synchronizes control of a shared resource. The lock manager may determine, for the lock identified in the lock release message, multiple processors contending to acquire the lock and select a particular processor among the multiple processors to acquire the lock.

Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.

Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: A method for connecting adjacent computing board devices. A source computing board may be provided. An optical engine attaches to the source computing board. A plurality of source optical connectors couples to the optical engine. A first optical connector may be positioned at a location on the source computing board for a first preset type of computing component on an adjacent computing board. A second optical connector may be positioned at a fixed coordinate related to the first optical connector on the source computing board.

Abstract: A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory container (105), the memory controller (105) composing a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: The system provides a photonic waveguide formed on a substrate and a plurality of steering mirrors within the photonic waveguide. The steering mirrors can be configured to direct a light beam between two or more computing components. A plurality of steering mirror supports are located within the waveguide having preset locations. The steering mirror supports are configured to enable the steering mirrors to be selectively repositioned at the preset steering mirror supports within the photonic waveguide to create varying configurations. The steering mirrors in the varying configurations direct one or more optical beams to form multiple connectivity channels between computing components within the photonic waveguide.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.