Abstract: A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M?1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.

Abstract: An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device.

Abstract: Methods and apparatus in a partitionable computing system. A state machine monitors the status of a partition or processor of the partitionable computing system. The state machine can include processor, a logic device, a register, and computer readable instructions.

Abstract: Methods and apparatus in a partitionable computing system. The system can include a computer readable medium comprising instructions configured to move an element of a first partition to a second partition.

Abstract: A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.

Abstract: Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.

Abstract: Distributing communications between paths, comprises providing a plurality of destinations, providing a plurality of communications paths such that each of the plurality of destinations can be accessed over each of the plurality of communications paths, defining destination addresses interleaved over the plurality of destinations, sending communications from a source to a plurality of the interleaved addresses, and selecting different ones of the plurality of paths for successive communications that are sent to addresses on different destinations, wherein the path for a communication is selected using at least a part of the address of the communication.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: Methods and apparatus in a partitionable computing system. A processor of a partition and a transmitter can configure and transmit a data packet that includes a source and a destination address. A routing device can have a port communication with the transmitter. The port can have a firewall associated therewith.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.

Abstract: Methods and apparatus in a partitionable computing system. A processor communicates with a packet former. The packet former can be configured to construct a data packet that can include security status information related to a partition or processor.

Abstract: Methods and apparatus in a partitionable computing system. A state machine monitors the status of a partition or processor system. The security status information can be communicated to a device controller to protect a register within the device controller.

Abstract: A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.

Abstract: A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.