Patents by Inventor Gary Howe
Gary Howe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250054812Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: December 29, 2023Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20250054767Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: April 25, 2024Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20240379768Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.Type: ApplicationFiled: May 12, 2023Publication date: November 14, 2024Inventors: Shumao ZHANG, Le ZHANG, Weifeng YE, Chih-Hsun HSU, David T. OR, Gary HOW, Yiyang WAN, Liqi WU, Jiang LU
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Method of Selective Metal Deposition Using Separated Reactant Activation and Plasma Discharging Zone
Publication number: 20240191354Abstract: Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.Type: ApplicationFiled: December 9, 2022Publication date: June 13, 2024Inventors: Ying-Bing JIANG, Joung Joo LEE, Xianmin TANG, Jiang LU, Avgerinos V. GELATOS, Dien-yeh WU, Weifeng YE, Yiyang WAN, Gary HOW, Joseph HERNANDEZ -
Patent number: 11915775Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.Type: GrantFiled: September 29, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Jack Riley, Scott Smith, Christian Mohr, Gary Howe, Joshua Alzheimer, Yoshinori Fujiwara, Sujeet Ayyapureddi, Randall Rooney
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Publication number: 20230401008Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.Type: ApplicationFiled: August 16, 2023Publication date: December 14, 2023Inventor: Gary Howe
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Publication number: 20230377892Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Yiyang WAN, Weifeng YE, Shumao ZHANG, Gary HOW, Jiang LU, Lei ZHOU, Dien-yeh WU, Douglas LONG, Avgerinos V. GELATOS, Ying-Bing JIANG, Rongjun WANG, Xianmin TANG, Halbert CHONG
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Patent number: 11670356Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).Type: GrantFiled: July 16, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Yoshinori Fujiwara, Harish V. Gadamsetty, Gary Howe, Dennis G. Montierth, Michael A. Shore, Jason M. Johnson
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Patent number: 11646095Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.Type: GrantFiled: March 6, 2020Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventors: Gary Howe, John E. Riley
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Publication number: 20230096291Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Jack Riley, Scott Smith, Christian Mohr, Gary Howe, Joshua Alzheimer, Yoshinori Fujiwara, Sujeet Ayyapureddi, Randall Rooney
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Publication number: 20230020753Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshinori Fujiwara, Harish V. Gadamsetty, Gary Howe, Dennis G. Montierth, Michael A. Shore, Jason M. Johnson
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Patent number: 11545199Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: GrantFiled: March 12, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
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Publication number: 20210280267Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.Type: ApplicationFiled: March 6, 2020Publication date: September 9, 2021Inventors: Gary Howe, John E. Riley
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Patent number: 11099774Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.Type: GrantFiled: August 30, 2017Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventor: Gary Howe
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Publication number: 20210201970Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
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Patent number: 10950282Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: GrantFiled: August 13, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
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Patent number: 10672496Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. Additionally, the memory device may include one or more counters to assist in accessing the memory cells of the memory array.Type: GrantFiled: October 24, 2017Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Joshua E. Alzheimer, Gary Howe, Harish N. Venkata
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Patent number: 10664173Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.Type: GrantFiled: January 30, 2018Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Gary Howe, Liang Chen, Daniel B. Penney
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Publication number: 20190371379Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
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Patent number: 10424356Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: GrantFiled: July 27, 2018Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather