Abstract: Systems, apparatuses, and methods for a non-target command in a multi-rank memory system are disclosed. A command is received by a first memory rank and a second memory rank. The first memory rank may be a target rank for the command, and the second memory rank may be a non-target rank for the command. The first memory rank performs a first operation responsive to the command, and the second memory rank performs a second operation different from the first operation responsive to the command. In some embodiments, the first memory rank receives an active pulse of a first chip select signal for the command and the second memory rank receives at least two active pulses of a second chip select signal for the command. In some embodiments, the command includes at least one rank encoding bit used to specify a target rank. The command may be an activate command.

Abstract: A memory device may have multiple storage modes. The memory array may be arranged differently for the storage modes. For the storage modes, the memory device may store information to correctly map logical addresses to physical memory locations that have been repaired. In some examples, additional fuses storing addresses for the storage modes are included. In some examples, additional fuses encoding address shift information are included. In some examples, a mode register write may initiate a broadcast operation to provide mapping information for the different storage modes. In some examples, the memory device may include additional logic circuits for shifting the addresses for the different storage modes.

Abstract: A memory device may have multiple storage modes. The memory array may be arranged differently for the storage modes. For the storage modes, the memory device may store information to correctly map logical addresses to physical memory locations that have been repaired. In some examples, additional fuses storing addresses for the storage modes are included. In some examples, additional fuses encoding address shift information are included. In some examples, a mode register write may initiate a broadcast operation to provide mapping information for the different storage modes. In some examples, the memory device may include additional logic circuits for shifting the addresses for the different storage modes.

Abstract: A memory device may have multiple storage modes. The memory array may be arranged differently for the storage modes. For the storage modes, the memory device may store information to correctly map logical addresses to physical memory locations that have been repaired. In some examples, additional fuses storing addresses for the storage modes are included. In some examples, additional fuses encoding address shift information are included. In some examples, a mode register write may initiate a broadcast operation to provide mapping information for the different storage modes. In some examples, the memory device may include additional logic circuits for shifting the addresses for the different storage modes.

Abstract: Systems, apparatuses, and methods for a non-target refresh operation in a multi-rank memory system are disclosed. A command is received by a first memory rank and a second memory rank. The first memory rank may be a target rank, and the second memory rank may be a non-target rank. The first memory rank performs a first operation responsive to the command, and the second memory rank performs a second operation different from the first operation responsive to the command, the second operation comprising a refresh operation. In some embodiments, the first memory rank receives an active pulse of a first chip select signal for the command and the second memory rank receives at least two active pulses of a second chip select signal for the command. In some embodiments, the command includes at least one rank encoding bit to specify a target rank. The command may be an activate command.

Abstract: A memory device may include a memory array organized into banks, which are organized into column planes with multiple column selects signals. The addresses for column select signals within a plane may be remapped to different column select signals within the plane by setting one or more swap bits. In some examples, two swap bits may be provided. In some examples, the swap bits may permit swapping of the two most significant bits of the column select address. One or both of the swap bits may be set. For example, the most significant bit, the next most significant bit, or both may be flipped.

Abstract: A memory device may have multiple storage modes. The memory array may be arranged differently for the storage modes. For the storage modes, the memory device may store information to correctly map logical addresses to physical memory locations that have been repaired. In some examples, additional fuses storing addresses for the storage modes are included. In some examples, additional fuses encoding address shift information are included. In some examples, a mode register write may initiate a broadcast operation to provide mapping information for the different storage modes. In some examples, the memory device may include additional logic circuits for shifting the addresses for the different storage modes.

Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

Abstract: Techniques for determining a refresh servicing rate of a memory device are disclosed. A refresh control circuit of the memory device determines that a refresh requirement is not met. The determination can be made, for example, based on a count value indicating refresh operations during a time period, using a shift register, or based on a queue of aggressor addresses. When the refresh requirement is not met, the refresh control circuit increases a refresh servicing rate. Increasing the refresh servicing rate may include applying a multiplier to a number of expected refreshes, or causing performance of background refresh operations until a stopping criterion is met. The refresh requirement may correspond to a number of expected refresh operations (e.g., background refresh operations) during a time period.

Abstract: Systems, apparatuses, and methods for a memory architecture using a column repeater are disclosed. A memory array includes a first portion and a second portion. A column decoder is coupled to the memory array, and a column repeater is coupled to the second portion of the memory array. The column decoder provides a column selection signal to the column repeater when a received address is associated with the second portion of the memory array, and the column repeater provides the column selection signal to one or more columns in the second portion of the memory array. In some implementations, the column repeater is disposed between the first portion and the second portion.

Abstract: Techniques for adjusting a frequency at which a memory controller polls a refresh flag are disclosed. Traffic counters are maintained to track traffic to portions of a memory device. A traffic balance is computed using the traffic counters, which indicates a distribution of the traffic to the portions of the memory device. For example, where access operations are performed equally in two halves of a memory bank, the traffic to the memory bank is equally balanced. In memory devices implementing background refresh traffic technology, high traffic balance may indicate that a memory device is likely to be adequately refreshed because opportunities for background refresh operations are evenly distributed. As a result, a memory controller may reduce the frequency at which a refresh flag of the memory is polled when the total traffic exceeds a threshold and when the traffic balance exceeds a threshold.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, one or more physical column planes may be selectively configured to store metadata. Depending on the amount of metadata to be stored, the column selects may be arranged into virtual column planes to allow data to be stored in physical column plane(s) used for metadata. The physical column planes may be arranged into virtual planes to store the data. Column select signals for physical column planes may be suppressed to facilitate the virtual planes. Different suppression schemes may be used based on the amount of metadata stored.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, one or more physical column planes may be selectively configured to store metadata. Depending on the amount of metadata to be stored, the column selects may be arranged into virtual column planes to allow data to be stored in physical column plane(s) used for metadata. The physical column planes may be arranged into virtual planes to store the data. Column select signals for physical column planes may be suppressed to facilitate the virtual planes. Different suppression schemes may be used based on the amount of metadata stored.

Abstract: A memory device includes a plurality of memory banks. The memory device receives a linked activation command along with a bank address which specifies a first one of the memory banks. While an access operation is performed on the first memory bank responsive to the linked activation command, a refresh operation is performed on a second memory bank responsive to the linked activation. The first and the second memory banks are part of a bank link group. A second linked activation command may be received a time after first linked activation command which is less than a refresh delay tRFCL as long as the second linked activation command is to a different bank link group.

Abstract: A memory device can operate in multiple powerdown modes. A first powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers completely (e.g., turn off). A second powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers incompletely (e.g., a reduced operational state). In a non-limiting nonexclusive embodiment, the second powerdown mode powers down the one or more CA input buffers by placing the one or more CA input buffers in a low bias current state.

Abstract: Apparatuses, systems, and methods for setting termination impedance based on encoding bits are disclosed. A memory receives an access command including one or more encoding bits, which may be received via one or more CA pins. Based on the one or more encoding bits and a setting in a mode register, the memory determines whether it is a target of the access command, and the memory applies a termination impedance based at least in part on the determination of whether it is the target of the access command. In various embodiments, the determination of whether the memory is the target can be performed in a single cycle.

Abstract: A memory has a bank with at least two row decoders each of which control at least two portions of the bank. Each word line has an associated access count which is stored along a word line coupled to a different row decoder. For example, if the memory receives an activate command and a row address that specifies a first word line associated with the first row decoder, then a second word line in a second portion associated with the second row decoder is also activated and an access count along the second word line is read out and updated. When an access is performed, the memory determines if a background refresh may be performed in a third portion also associated with the second row decoder.

Abstract: A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.

Abstract: A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.

Abstract: A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.