Patents by Inventor Gary Howe

Gary Howe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190235760
    Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Inventors: Gary Howe, Liang Chen, Daniel B. Penney
  • Patent number: 10318238
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Gary Howe
  • Publication number: 20190156871
    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.
    Type: Application
    Filed: July 27, 2018
    Publication date: May 23, 2019
    Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
  • Publication number: 20190122744
    Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventors: Joshua E. Alzheimer, Gary Howe, Harish N. Venkata
  • Publication number: 20190065106
    Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventor: Gary Howe
  • Publication number: 20180357041
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Brian Huber, Gary Howe
  • Patent number: 10120647
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 6, 2018
    Inventors: Brian Huber, Gary Howe
  • Patent number: 10068648
    Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Gary Howe
  • Publication number: 20170357482
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 14, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Brian Huber, Gary Howe
  • Patent number: 9778903
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Gary Howe
  • Patent number: 9196321
    Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Brian W. Huber, Vijay Vankayala, Brian Gross, Gary Howe, Roy E. Greeff
  • Publication number: 20150098285
    Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Brian W. Huber, Vijay Vankayala, Brian Gross, Gary Howe, Roy E. Greeff
  • Patent number: 8958256
    Abstract: Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vijayakrishna J. Vankayala, Gary Howe, John Winegard, Vipul Surlekar
  • Publication number: 20130265834
    Abstract: Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Vijayakrishna J. Vankayala, Gary Howe, John Winegard, Vipul Surlekar
  • Publication number: 20050141308
    Abstract: The present technique relates to a method and apparatus for detecting a change in a data signal at a buffer device. In the buffer device, first stage comparators may be adapted to receive a data signal and either a first voltage timing reference (VTR) signal or a complimentary VTR signal. The first stage comparators may each deliver an output signal to second stage comparators. Each of the second stage comparators receives the output signal from each of the first stage comparators. From the first stage comparator signals, the second stage comparators produce an output signal, such as a first output signal and a second output signal. These output signals from the second stage comparators are differential signals.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventor: Gary Howe