Patents by Inventor Gary J. Ballantyne
Gary J. Ballantyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150055514Abstract: A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.Type: ApplicationFiled: October 1, 2014Publication date: February 26, 2015Inventor: Gary J. Ballantyne
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Patent number: 8963611Abstract: Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.Type: GrantFiled: October 16, 2009Date of Patent: February 24, 2015Assignee: QUALCOMM IncorporatedInventors: Puay Hoe See, Gary J. Ballantyne, Gurkanwal Singh Sahota, Aristotele Hadjichristos, Alberto Cicalini
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Patent number: 8880010Abstract: A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.Type: GrantFiled: December 30, 2009Date of Patent: November 4, 2014Assignee: QUALCOMM IncorporatedInventor: Gary J. Ballantyne
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Patent number: 8588720Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.Type: GrantFiled: December 15, 2009Date of Patent: November 19, 2013Assignee: QUALCOMM IncorproatedInventors: Gary J. Ballantyne, Jifeng Geng, Bo Sun
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Patent number: 8531219Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.Type: GrantFiled: April 19, 2013Date of Patent: September 10, 2013Assignee: QUALCOMM IncorporatedInventors: Jeremy D. Dunworth, Gary J. Ballantyne, Bhushan S. Asuri, Jifeng Geng, Gurkanwal S. Sahota
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Publication number: 20130229212Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.Type: ApplicationFiled: April 19, 2013Publication date: September 5, 2013Applicant: Qualcomm IncorporatedInventors: Jeremy D. Dunworth, Gary J. Ballantyne, Bhushan S. Asuri, Jifeng Geng, Gurkanwal S. Sahota
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Patent number: 8446191Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).Type: GrantFiled: December 7, 2009Date of Patent: May 21, 2013Assignee: Qualcomm IncorporatedInventors: Jeremy D. Dunworth, Gary J. Ballantyne, Bhushan S. Asuri, Jifeng Geng, Gurkanwal S. Sahota
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Patent number: 8339165Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.Type: GrantFiled: December 7, 2009Date of Patent: December 25, 2012Assignee: QUALCOMM IncorporatedInventors: Jeremy D. Dunworth, Gary J. Ballantyne, Bhushan S. Asuri
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Patent number: 8098103Abstract: Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.Type: GrantFiled: June 12, 2009Date of Patent: January 17, 2012Assignee: QUALCOMM IncorporatedInventors: Daniel F. Filipovic, Gary J. Ballantyne, Jifeng Geng
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Patent number: 8076960Abstract: A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.Type: GrantFiled: April 29, 2009Date of Patent: December 13, 2011Assignee: QUALCOMM IncorporatedInventors: Jifeng Geng, Gary J. Ballantyne, Daniel F. Filipovic
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Publication number: 20110158346Abstract: A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: QUALCOMM IncorporatedInventor: Gary J. Ballantyne
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Publication number: 20110143689Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: QUALCOMM IncorporatedInventors: Gary J. Ballantyne, Jifeng Geng, Bo Sun
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Publication number: 20110133794Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).Type: ApplicationFiled: December 7, 2009Publication date: June 9, 2011Applicant: QUALCOMM IncorporatedInventors: JEREMY D. DUNWORTH, GARY J. BALLANTYNE, BHUSHAN S. ASURI, JIFENG GENG, GURKANWAL S. SAHOTA
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Publication number: 20110133799Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.Type: ApplicationFiled: December 7, 2009Publication date: June 9, 2011Applicant: QUALCOMM IncorporatedInventors: Jeremy D. Dunworth, Gary J. Ballantyne, Bhushan S. Asuri
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Publication number: 20100327932Abstract: Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Applicant: QUALCOMM IncorporatedInventors: Vladimir Aparin, Gary J. Ballantyne
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Publication number: 20100321086Abstract: Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.Type: ApplicationFiled: October 16, 2009Publication date: December 23, 2010Applicant: QUALCOMM INCORPORATEDInventors: Puay Hoe See, Gary J. Ballantyne, Gurkanwal Singh Sahota, Aristotele Hadjichristos, Alberto Cicalini
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Publication number: 20100315169Abstract: Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: QUALCOMM IncorporatedInventors: Daniel F. Filipovic, Gary J. Ballantyne, Jifeng Geng
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Publication number: 20100277211Abstract: A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Applicant: QUALCOMM IncorporatedInventors: Jifeng Geng, Gary J. Ballantyne, Daniel F. Filipovic
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Patent number: 7031678Abstract: This disclosure is directed to techniques for voice and data transmission from a wireless communication device, such as mobile telephone handset. In accordance with the disclosure, a wireless communication provides a hybrid coupler that permits voice and data calls to be combined for transmission over a common air interface. When increased transmit power is required, the wireless communication device prioritizes the voice call over the data call. In this case, the voice call is sent over both the voice output branch and the data output branch, taking advantage of the power amplifier in each output branch chain to achieve a greater overall transmit power for the voice transmission. In this manner, the mobile subscriber unit independently and simultaneously handles data and voice calls under ordinary circumstances, but drops the data call and combines the voice and data output branches for voice transmission when increased transmit power is required for the voice transmission.Type: GrantFiled: July 15, 2003Date of Patent: April 18, 2006Assignee: Qualcomm Inc.Inventor: Gary J. Ballantyne
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Patent number: 6983024Abstract: A quadra-polar modulator that is simple to implement and also provides good noise performance. The quadra-polar modulator includes four amplitude modulators and a combiner. Each amplitude modulator modulates a respective carrier signal with a respective input signal to provide a respective output signal. The combiner then combines the four output signals from the four amplitude modulators to provide a modulated signal. Each amplitude modulator may be implemented with a switching amplifier, such as a supply modulated class E amplifier. Two input signals are obtained by summing separately an inphase (I) modulating signal and an inverted I modulating signal with an offset value. The other two input signals are obtained by summing separately a quadrature (Q) modulating signal and an inverted Q modulating signal with the offset value. The offset value can be selected based on the expected magnitude of the modulating signals. The four carrier signals are in quadrature to each other.Type: GrantFiled: March 18, 2003Date of Patent: January 3, 2006Assignee: Qualcomm Inc.Inventor: Gary J. Ballantyne