Abstract: The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.

Abstract: The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.

Abstract: In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process:

Abstract: In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process:

Abstract: The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.

Abstract: The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.

Abstract: In its several embodiments, this invention discloses novel processes to prepare the compounds of formula II and formula IV:

Abstract: In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process:

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: In its several embodiments, this invention discloses novel processes to prepare the compounds of formula II and formula IV: 1

Abstract: In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process: 1

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: A method and apparatus for reducing power consumption by gallium arsenide integrated circuits divides the integrated circuit into higher and lower frequency sections. The high frequency sections require a substantial portion of the system clock period to resolve their longest combinatorial paths. The lower frequency sections require a relatively small portion of the system clock period to resolve their longest combinatorial logic paths. The combinatorial logic paths of each of such lower frequency sections are designed using logic gates which are capable of being decoupled from the chip power supply by way of a power enable input. Edge triggered memory circuits such as flip-flops are also designed using the reduced power logic gates, except for their cross-coupled outputs so that they may retain their state.

Abstract: Disclosed are a process and intermediates of the formulae ##STR1## wherein X.sup.- is halide, BF.sub.4.sup.-, R.sup.3 SO.sub.3.sup.-, wherein R.sup.3 is C.sub.1 -C.sub.6 alkyl, CF.sub.3, C.sub.1 -C.sub.6 alkylphenyl or phenyl, and Q is a group of the formula ##STR2## wherein R is C.sub.1 -C.sub.6 alkyl; useful for preparing benzazepine intermediates of the formula ##STR3## These benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.

Abstract: Disclosed are a process and intermediates of the formula ##STR1## wherein R is --CH.sub.3 or --C(O)--OR.sup.1, and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5 ; or the formula ##STR2## wherein: R.sup.2 is H or OH, R is --C(O)OR.sup.1 and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5, or where R.sup.2 is H, R can also be CH.sub.3 ; for preparing benzazepine intermediates of the formula ##STR3## The benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.

Abstract: Disclosed are a process and intermediates of the formulae ##STR1## wherein X.sup.- is halide, BF.sub.4.sup.-, R.sup.3 SO.sub.3.sup.-, wherein R.sup.3 is C.sub.1 -C.sub.6 alkyl, CF.sub.3, C.sub.1 -C.sub.6 alkylphenyl or phenyl, and Q is a group of the formula ##STR2## wherein R is C.sub.1 -C.sub.6 alkyl; useful for preparing benzazepine intermediates of the formula ##STR3## These benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.

Abstract: Disclosed are a process and intermediates of the formula ##STR1## wherein R is --CH.sub.3 or --C(O)--OR.sup.1, and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5 ; or the formula ##STR2## wherein: R.sup.2 is H or OH, R is --C(O)OR.sup.1 and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5, or where R.sup.2 is H, R can also be CH.sub.3 ; for preparing benzazepine intermediates of the formula ##STR3## The benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.