Patents by Inventor Gary M. Lee

Gary M. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5353448
    Abstract: A water recycling system primarily adapted for use in shower facilities enabling the user to increase both the time duration of a shower and the quantity of water experienced by a user, by maintaining water in a semi-closed system, while both maintaining water and energy conservation. The system preferably operates with fresh and recirculated hot water. The system utilizes spent hot shower water located in the catchment area of a shower or tub and recycles this water to one or more spray heads located at or in the proximity of the regular water dispensing head or so-called "spray head" of that shower. A selected water temperature can be maintained by periodically introducing fresh water or continuously introducing the fresh water at a very low flow rate from a fresh water source, and mixing that water with the recycled water from a water catchment area. Recycled water can also be re-heated and issued again.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: October 11, 1994
    Inventor: Gary M. Lee
  • Patent number: 4798979
    Abstract: A digital logic circuit using Schottky diodes as the nonlinear logic element, a single power supply and an E-mode MESFET as an inverter in the open drain configuration. Temperature compensation of the threshold voltage of the E-mode FET is provided. The circuit is particularly suited for use with a GaAs substrate.
    Type: Grant
    Filed: September 23, 1986
    Date of Patent: January 17, 1989
    Assignee: Honeywell Inc.
    Inventors: Gary M. Lee, Andrzej Peczalski
  • Patent number: 4798978
    Abstract: A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.
    Type: Grant
    Filed: April 30, 1987
    Date of Patent: January 17, 1989
    Assignee: Gain Electronics Corporation
    Inventors: Gary M. Lee, Charles M. Lee, George S. LaRue
  • Patent number: 4737837
    Abstract: An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.
    Type: Grant
    Filed: November 27, 1985
    Date of Patent: April 12, 1988
    Assignee: Honeywell Inc.
    Inventor: Gary M. Lee