Patents by Inventor Gary Shen
Gary Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210347810Abstract: The invention relates to sterol esters and methods for producing purified sterols that can be utilized in methods for producing a lipid nanoparticle.Type: ApplicationFiled: September 19, 2019Publication date: November 11, 2021Inventors: Gabor BUTORA, Jin LIM, Gary SHEN, Alison VOLKERT
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Patent number: 9054025Abstract: A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.Type: GrantFiled: June 4, 2009Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen, Shun-Jang Liao
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Publication number: 20140334090Abstract: A filled polymeric composition of high flowability suitable for thin wall (<1 mm thickness) molding, the composition including (a) from 10 to 50 wt % of a reinforcing filler; (b) from 1 to 10 wt % of a polyamide or from 5 to 20 wt % of a liquid crystal polymer (LCP) as a flow promoter; and the balance being a polyetherimide (PEI) resin. Composites including an injection molded substrate having a thickness of 0.4-0.8 mm, formed of the composition, and at least one coating thereon. The coating can be a metal or an acrylate coating.Type: ApplicationFiled: December 31, 2012Publication date: November 13, 2014Applicant: SABIC INNOVATIVE PLASTICS IP B.V. et alInventors: Gary Shen, Yangang Yan
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Patent number: 8598630Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.Type: GrantFiled: May 21, 2009Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gary Shen, Ming-Yuan Wu, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang
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Patent number: 8390072Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.Type: GrantFiled: June 9, 2011Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
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Patent number: 8349680Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.Type: GrantFiled: August 6, 2009Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Yu Chao Lin
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Patent number: 8286114Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.Type: GrantFiled: August 2, 2007Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang
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Publication number: 20110233683Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
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Patent number: 7985690Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: GrantFiled: June 4, 2009Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7981801Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.Type: GrantFiled: April 14, 2009Date of Patent: July 19, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
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Patent number: 7923321Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.Type: GrantFiled: June 19, 2009Date of Patent: April 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen
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Publication number: 20100311231Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: ApplicationFiled: June 4, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7732516Abstract: A composition is disclosed, comprising, based on the total weight of the composition, from 20 to 60 wt. % of a polyimide having a glass transition temperature above 180° C.; from 10 to 30 wt. % a polyester-polycarbonate copolymer; from 30 to 60 wt. % of a reinforcing filler; and at least two flame retardant additives selected from the group consisting of from 0.01 to 0.5 wt. % of a first sulfonate salt, from 0.01 to 0.5 wt. % of a second sulfonate salt, from 0.5 to 5 wt. % of a siloxane copolymer, and combinations thereof. An article molded from the composition attains an improved UL94 rating, as compared to an article molded from the same composition without the at least two flame retardant additives.Type: GrantFiled: January 31, 2008Date of Patent: June 8, 2010Assignee: Sabic Innovative Plastics IP B.V.Inventors: Gary Shen, Lily Pan
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Publication number: 20100112732Abstract: A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.Type: ApplicationFiled: June 4, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen, Shun-Jang Liao
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Publication number: 20100112798Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.Type: ApplicationFiled: June 19, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen
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Publication number: 20100084715Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.Type: ApplicationFiled: May 21, 2009Publication date: April 8, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gary Shen, Ming-Yuan Wu, Chiung-Han Yeh, Kong-Beng Thei, Harry Chuang
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Publication number: 20100065915Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.Type: ApplicationFiled: April 14, 2009Publication date: March 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
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Publication number: 20100048013Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.Type: ApplicationFiled: August 6, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Y. C. Lin
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Publication number: 20090197999Abstract: A composition is disclosed, comprising, based on the total weight of the composition, from 20 to 60 wt. % of a polyimide having a glass transition temperature above 180° C.; from 10 to 30 wt. % a polyester-polycarbonate copolymer; from 30 to 60 wt. % of a reinforcing filler; and at least two flame retardant additives selected from the group consisting of from 0.01 to 0.5 wt. % of a first sulfonate salt, from 0.01 to 0.5 wt. % of a second sulfonate salt, from 0.5 to 5 wt. % of a siloxane copolymer, and combinations thereof. An article molded from the composition attains an improved UL94 rating, as compared to an article molded from the same composition without the at least two flame retardant additives.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Gary Shen, Lily Pan
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Publication number: 20080263492Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.Type: ApplicationFiled: August 2, 2007Publication date: October 23, 2008Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang