Abstract: An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal during a predetermined number of cycles of the external signal, or the number of cycles of the external signal during a predetermined number of cycles of the clock signal; (c) store a trim value in the integrated circuit, the trim value having been determined on the basis of the determined number of cycles; and (d) use the trim value to control the internal clock frequency.

Abstract: An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: The present invention provides an ink ejection type printhead having a plurality of ink ejection devices and a central axis, the ink ejection devices arranged in a series of groups, each of the groups generally extending along at least partially curved radial lines.

Abstract: An integrated circuit comprising: at least one active device that outputs light during a change in state of the at least one device during operation; a clock circuit configured to output a clock signal to the at least one active device, the clock signal rate being varied so as to hinder optical detection of a pattern of the light during operation of the at least one active device.

Abstract: An integrated circuit comprising a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit, wherein the integrated circuit is configured to enable multi-word writes to the non-volatile memory, the power detection unit being configured to: monitor a quality of power supplied to the input; and in the event the quality of the power drops below a predetermined threshold, preventing subsequent words in any multi-word write currently being performed from being written to the memory.

Abstract: An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to: monitor a quality of power supplied to the input; and in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit's ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power.

Abstract: An inkjet printhead with a substrate having a plurality of inkjet nozzles formed in the substrate; the inkjet nozzles being arranged in groups, each group extending generally along a respective line along the substrate; wherein, at least two of the lines are intersecting, provides a printhead design that is well suited to use in a universal pen capable of changing the attributes of the marks it makes on a surface.

Abstract: A phase shift keying (PSK) receiver includes a limiter and a first receive filter. In order to compensate for distortion introduced by the limiter, the amplitude limited signal is subjected to equalization prior to being supplied to the first receive filter. Equalization is performed by receiving a digital input signal representing an output of the limiter, estimating an amplitude modulation component as a function of the digital input signal, and generating the equalized signal by modifying the digital input signal as a function of the estimated amplitude modulation component. The amplitude modulation component may be estimated by generating a filtered signal by filtering the digital input signal in accordance with a filtering characteristic that is substantially identical to a filtering characteristic of the first receive filter, and then generating the amplitude modulation component by measuring the amplitude of the filtered signal.

Abstract: An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal during a predetermined number of cycles of the external signal, or the number of cycles of the external signal during a predetermined number of cycles of the clock signal; (c) store a trim value in the integrated circuit, the trim value having been determined on the basis of the determined number of cycles; and (d) use the trim value to control the internal clock frequency.

Abstract: An ink ejection type printhead having a plurality of ink ejection devices around a central axis, the ink ejection devices arranged in a series of groups generally extending along non parallel lines (1370-1381). The lines may be curved. The illustrated form of the printhead is suitable for use in a pen, or cartridge for a pen, as an alternative to a conventional nib or point of a pen or pencil.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: A method of demodulating an FM carrier wave and a demodulating circuit are described which utilize a gain control circuit. An output is supplied from the gain control circuit to a phase locked loop circuit tuned to a selected carrier wave frequency. A first output of the phase locked loop circuit is used to generate a tuned gain control signal dependent on the amplitude of the input FM carrier wave to which the phase locked loop is tuned and the tuned gain control signal is used to control the gain of the gain control circuit.

Abstract: Apparatus for setting up the tuning frequency of a phase locked loop is provided which utilises the voltage controlled oscillator of the phase locked loop itself. The apparatus includes signal translation circuitry which can provide a control voltage to the VCO of the phase locked loop dependent on a tuning voltage which is alterable in response to the frequency of the signal output by the VCO.