Abstract: There is a need for more effective and efficient predictive data analysis solutions and/or more effective and efficient solutions for generating an emotional sentiment score without the use of labelled data. In one example, embodiments comprise receiving an input text sequence, generating an intermediate emotional sentiment score object based at least in part on the input text sequence and by utilizing an emotional sentiment machine learning model, generating an overall emotional sentiment score based at least in part on the intermediate sentiment score object and by utilizing an emotional sentiment score transformation object, and performing one or more prediction-based actions based at least in part on the overall emotional sentiment score.

Abstract: Described are novel HIV-binding peptides and methods of using them for treating or preventing HIV infection and/or the development of AIDS.

Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.

Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.

Abstract: Provided are highly conserved antigens and epitopes of HIV that can be used in vaccines and to produce bindings proteins (e.g., antibodies) for detecting, treating, preventing, or reducing the risk of HIV infection and the development of AIDS.

Abstract: Provided are highly conserved antigens and epitopes of SARS-CoV-2 that can be used in vaccines and to produce bindings proteins (e.g.

Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.

Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.

Abstract: The present disclosure provides an apparatus and method for sharing content. A method provided in the present disclosure comprises receiving a message to request to join a content sharing group from a second device while a third device included in the content sharing group transmits first content shared in the content sharing group to a fourth device included in the content sharing group, adding the second device to the content sharing group, and permitting the second device to access the first content.

Abstract: The present disclosure provides an apparatus and method for sharing content. A method provided in the present disclosure comprises receiving a message to request to join a content sharing group from a second device while a third device included in the content sharing group transmits first content shared in the content sharing group to a fourth device included in the content sharing group, adding the second device to the content sharing group, and permitting the second device to access the first content.

Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Abstract: In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.