Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may comprise, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One method includes generating a transmit signal by passing a pre-driver transmit signal through a transmit driver. An echo cancellation signal is generated by passing the pre-driver transmit signal through an echo cancellation driver. A residual echo signal is generated by passing a pre-driver residual echo cancellation signal through a residual echo cancellation driver. The transceiver simultaneously transmits the transmit signal, and receiving the receive signal. At least a portion of an echo signal of the receive signal is canceled by summing the echo cancellation signal with the receive signal. At least another portion of the cancellation echo signal of the receive signal is canceled by summing the residual echo cancellation signal with the receive signal.

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One embodiment of an apparatus includes a transceiver that simultaneously transmits a transmit signal and receives a receive signal. The transceiver includes a transmit DAC that generates the transmit signal based on a transmit digital signal stream. The transmit DAC includes a plurality of transmit DAC circuit elements, and a plurality of transmit DAC switches that control which of the plurality of transmit DAC circuit elements contribute to generating the transmit signal. The transceiver additionally includes an echo cancellation DAC that generates an echo cancellation signal based on the transmit digital signal stream.

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One embodiment of an apparatus includes a transceiver that simultaneously transmits a transmit signal and receives a receive signal. The transceiver includes a transmit DAC that generates the transmit signal based on a transmit digital signal stream. The transmit DAC includes a plurality of transmit DAC circuit elements, and a plurality of transmit DAC switches that control which of the plurality of transmit DAC circuit elements contribute to generating the transmit signal. The transceiver additionally includes an echo cancellation DAC that generates an echo cancellation signal based on the transmit digital signal stream.

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One method includes generating a transmit signal by passing a pre-driver transmit signal through a transmit driver. An echo cancellation signal is generated by passing the pre-driver transmit signal through an echo cancellation driver. A residual echo signal is generated by passing a pre-driver residual echo cancellation signal through a residual echo cancellation driver. The transceiver simultaneously transmits the transmit signal, and receiving the receive signal. At least a portion of an echo signal of the receive signal is canceled by summing the echo cancellation signal with the receive signal. At least another portion of the cancellation echo signal of the receive signal is canceled by summing the residual echo cancellation signal with the receive signal.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Abstract: Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

Abstract: Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

Abstract: In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Abstract: In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

Abstract: In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

Abstract: In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.