Patents by Inventor Gaurav Chawla
Gaurav Chawla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10078454Abstract: Methods and systems for improved access to storage resources include installing a virtual storage appliance as a virtual machine on a hypervisor. The virtual storage appliance installs itself as a virtual PCI-E device and communicates with guest operating systems of the hypervisor using direct memory access via a PCI-E non-transparent bridge. The storage virtual appliance provides access to local and external storage resources with very high performance to applications running under the guest operating system, thereby overcoming performance barriers associated with native hypervisor driver models.Type: GrantFiled: June 15, 2016Date of Patent: September 18, 2018Assignee: Dell Products L.P.Inventors: Gaurav Chawla, Michael Karl Molloy, Robert Wayne Hormuth
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Patent number: 10044115Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.Type: GrantFiled: December 23, 2015Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla
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Patent number: 9948567Abstract: An Ethernet device includes receive buffers and transmit buffers of a port, and a processor. The buffers are each associated with a respective class of service. The processor operates to determine a current buffer utilization in a receive buffer, determine that the current buffer utilization is different than a buffer threshold for the receive buffer, determine a data rate limit for the class of service associated with the receive buffer based upon the difference between the current buffer utilization and the buffer threshold, and send a data rate limit frame to another device coupled to the port. The data rate limit frame includes the data rate limit for the class of service.Type: GrantFiled: February 29, 2016Date of Patent: April 17, 2018Assignee: DELL PRODUCTS, LPInventors: Hendrich M. Hernandez, Gaurav Chawla, Robert L. Winter
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Patent number: 9942158Abstract: An information handling system (IHS) network includes a switch IHS that coupled together a plurality of server IHSs. A source software-defined (SD) virtual appliance is located on one of the plurality of server IHSs. A destination SD virtual appliance is located on one of the plurality of server IHSs. An SD network controller is located on at least one of the plurality of server IHSs. The SD network controller is configured to receive a data traffic flow identifier and policy information that is associated with at least one data traffic flow policy from the source SD virtual appliance. The SD network controller determines a plurality of ports located between the source SD virtual appliance and the destination SD virtual appliance using the data traffic flow identifier. The SD network controller then configures each of the plurality of ports using the at least one data traffic flow policy.Type: GrantFiled: September 25, 2014Date of Patent: April 10, 2018Assignee: Dell Products L.P.Inventors: Sudhir Vittal Shetty, Gaurav Chawla, Joseph L. White
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Publication number: 20180019558Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 26, 2017Publication date: January 18, 2018Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
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Publication number: 20170366470Abstract: Disclosed herein are techniques for identifying computing resources specified by a representation of a computing service. In some implementations, a request to analyze a computing service provided via a computing environment may be received. The computing service may have an activated state in which the computing service is available for use and a deactivated state in which the computing service is not available for use. The computing environment may comprise a plurality of computing resources each defining a variable unit of computing functionality within the computing environment. Each computing resource may be associated with a respective parameter corresponding with a respective parameter value that specifies a level of the variable unit of computing functionality defined by the computing resource. The computing service may be represented by a metadata model comprising a plurality of nodes, at least some of which specify a respective one or more of the parameter values.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Inventors: Nathan Jensen-Horne, Dileep Burki, Walter Sims Harley, Matthew Small, Kenneth Douglas Scott, David Andrew Brooks, Prasad Peddada, Hemang Patel, Gaurav Chawla, Theresa Vietvu, Shriman Gurram
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Patent number: 9848510Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.Type: GrantFiled: December 19, 2014Date of Patent: December 19, 2017Assignee: Intel CorporationInventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
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Patent number: 9780510Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 26, 2014Date of Patent: October 3, 2017Assignee: INTEL CORPORATIONInventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
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Patent number: 9781049Abstract: Disclosed herein are techniques for identifying computing resources specified by a representation of a computing service. In some implementations, a request to analyze a computing service provided via a computing environment may be received. The computing service may have an activated state in which the computing service is available for use and a deactivated state in which the computing service is not available for use. The computing environment may comprise a plurality of computing resources each defining a variable unit of computing functionality within the computing environment. Each computing resource may be associated with a respective parameter corresponding with a respective parameter value that specifies a level of the variable unit of computing functionality defined by the computing resource. The computing service may be represented by a metadata model comprising a plurality of nodes, at least some of which specify a respective one or more of the parameter values.Type: GrantFiled: April 26, 2011Date of Patent: October 3, 2017Assignee: salesforce.com, inc.Inventors: Nathan Jensen-Horne, Dileep Burki, Walter Sims Harley, Matthew Small, Kenneth Douglas Scott, David Andrew Brooks, Prasad Peddada, Hemang Patel, Gaurav Chawla, Theresa Vietvu, Shriman Gurram
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Patent number: 9781069Abstract: A gratuitous address resolution protocol frame is sent from an information handling system upon detection of VLAN status change the information handling system. A status flag included in the address resolution protocol frame provides a switch that receives the frame with the status change, such as the addition or removal of a VLAN at the information handling system.Type: GrantFiled: April 2, 2015Date of Patent: October 3, 2017Assignee: DELL PRODUCTS L.P.Inventors: Hendrich Hernandez, Gaurav Chawla, Robert Winter
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Publication number: 20170187147Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla
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Patent number: 9640880Abstract: A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin axial cable that includes a first conductor and second conductor, a first insulator that surrounds the first conductor, and a second insulator that surrounds the second conductor. The twin axial cable further includes a ground shield that surrounds the first and second insulator. The first conductor is electrically connected to one conductive pad and the second conductor is electrically connected to another of the conductive pads. The ground shield is electrically connected to the grounding pad. A shielding structure is mounted to the substrate and is electrically connected to the grounding pad. The shielding structure includes a cap and a plurality of sidewalls extending from the cap to the substrate. The twin axial cable is positioned between the side walls.Type: GrantFiled: July 1, 2014Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Donald T. Tran, Jeffrey Lee, Gaurav Chawla
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Patent number: 9626324Abstract: Methods and systems for I/O acceleration on a virtualized information handling system include loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation.Type: GrantFiled: July 8, 2014Date of Patent: April 18, 2017Assignee: Dell Products L.P.Inventors: Gaurav Chawla, Robert Wayne Hormuth, Michael Karl Molloy, Shyam T. Iyer
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Patent number: 9615483Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.Type: GrantFiled: September 12, 2014Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan
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Patent number: 9603276Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.Type: GrantFiled: December 26, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
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Patent number: 9575926Abstract: A network device includes a port coupled to a device, another port coupled to another device, and an access control list with an access control entry that causes the network device to permit log in frames to be forwarded from the first device to the second device. The network device receives a frame addressed to the second device and determines the frame type. If the frame type is a log in frame, then the frame is forwarded to the second device and another access control entry is added to the access control list. The second access control entry causes the network device to permit data frames to be forwarded from the first device to the second device. If not, then the frame is dropped based upon the first access control entry.Type: GrantFiled: March 11, 2013Date of Patent: February 21, 2017Assignee: DELL PRODUCTS, LPInventors: Saikrishna M. Kotha, Gaurav Chawla
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Publication number: 20170027377Abstract: An apparatus includes a body, a removable first container for water for positioning on the body, a boiler within the body receives water from the first container, a heater adjacent to the boiler heats the water in accordance with at least one preparation parameter. The apparatus further includes a removable second container that is a combination milk carafe and boiler for positioning on the body and a separate heater adjacent to the milk carafe and boiler for heating the milk in accordance with at least one preparation parameter. A filter and a dispensing valve are controlled electronically. An interface and display for entering brewing parameters and a microcomputer for the controlling the apparatus.Type: ApplicationFiled: July 27, 2016Publication date: February 2, 2017Applicant: CAMELLIA LABS INCInventors: GAURAV CHAWLA, MATT LEANSE, PETER A. RELAN
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Patent number: 9490560Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.Type: GrantFiled: December 19, 2014Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Gaurav Chawla, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
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Patent number: 9478881Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.Type: GrantFiled: March 9, 2015Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Zhichao Zhang, Gaurav Chawla, Rajasekaran Swaminathan, Kemal Aygun, Li Sun
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Patent number: D800487Type: GrantFiled: January 14, 2016Date of Patent: October 24, 2017Assignee: Camellia Labs Inc.Inventors: Gaurav Chawla, Matt Leanse, Peter A. Relan