Patents by Inventor Gaurav Chawla

Gaurav Chawla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160299702
    Abstract: Methods and systems for improved access to storage resources include installing a virtual storage appliance as a virtual machine on a hypervisor. The virtual storage appliance installs itself as a virtual PCI-E device and communicates with guest operating systems of the hypervisor using direct memory access via a PCI-E non-transparent bridge. The storage virtual appliance provides access to local and external storage resources with very high performance to applications running under the guest operating system, thereby overcoming performance barriers associated with native hypervisor driver models.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Gaurav Chawla, Michael Karl Molloy, Robert Wayne Hormuth
  • Publication number: 20160276759
    Abstract: A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin axial cable that includes a first conductor and second conductor, a first insulator that surrounds the first conductor, and a second insulator that surrounds the second conductor. The twin axial cable further includes a ground shield that surrounds the first and second insulator. The first conductor is electrically connected to one conductive pad and the second conductor is electrically connected to another of the conductive pads. The ground shield is electrically connected to the grounding pad. A shielding structure is mounted to the substrate and is electrically connected to the grounding pad. The shielding structure includes a cap and a plurality of sidewalls extending from the cap to the substrate. The twin axial cable is positioned between the side walls.
    Type: Application
    Filed: July 1, 2014
    Publication date: September 22, 2016
    Inventors: Donald T. Tran, Jeffrey Lee, Gaurav Chawla
  • Publication number: 20160268710
    Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Zhichao Zhang, Gaurav Chawla, Rajasekaran Swaminathan, Kemal Aygun, Li Sun
  • Publication number: 20160254629
    Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2014
    Publication date: September 1, 2016
    Applicant: Intel Corporation
    Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
  • Patent number: 9405566
    Abstract: Methods and systems for improved access to storage resources include installing a virtual storage appliance as a virtual machine on a hypervisor. The virtual storage appliance installs itself as a virtual PCI-E device and communicates with guest operating systems of the hypervisor using direct memory access via a PCI-E non-transparent bridge. The storage virtual appliance provides access to local and external storage resources with very high performance to applications running under the guest operating system, thereby overcoming performance barriers associated with native hypervisor driver models.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: August 2, 2016
    Assignee: Dell Products L.P.
    Inventors: Gaurav Chawla, Michael Karl Molloy, Robert Wayne Hormuth
  • Publication number: 20160197775
    Abstract: A Data Center Bridged (DCB) Information Handling System (IHS) network include a plurality of switch IHSs that are connected together to provide the IHS network, and a management IHS coupled to each of the plurality of switch IHSs through a management network. The management IHS is configured to identify a plurality of data traffic flows and, for each identified data traffic flow, to determine a flow path through the IHS network. The flow paths include at least some of the plurality of switch IHSs, and the management IHS provides configuration information to each of the switch IHSs included in a flow path such that a quality of service (QoS) is provided for the data traffic flow along that flow path through the DCB IHS network according to the configuration information. Thus, the systems and methods utilize flow based networking to configure and manage DCB IHS networks.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Gaurav Chawla, Rajesh Narayanan, Shyamkumar T. Iyer
  • Patent number: 9385457
    Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
  • Patent number: 9385444
    Abstract: An apparatus comprises a socket for an integrated circuited (IC), wherein the socket includes a socket body that includes a plurality of land grid array contacts for contacting the IC, an alignment mechanism, and a locking mechanism, and a cover for the socket, wherein the cover is vertically alignable with the alignment mechanism of the socket body and laterally slidable over the grid array contacts upon alignment to engage the locking mechanism of the socket body.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Vijaykumar Krithivasan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley
  • Publication number: 20160190717
    Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
  • Publication number: 20160190716
    Abstract: Some forms relate to a socket having a housing. A first receiving pin field is formed as part of the housing. The first pin receiving field includes a first plurality of electrical contacts. A second receiving pin field is formed as part of the housing. The second pin field includes a second plurality of electrical contacts. An actuation mechanism is configured to engage the first plurality electrical contacts with a first set of pins on a first electronic package and the second plurality electrical contacts with a second set of pins on a second electronic package.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Kuang Liu, Gregorio Murtagian, David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado
  • Publication number: 20160183375
    Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
  • Publication number: 20160181714
    Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: GAURAV CHAWLA, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
  • Publication number: 20160182389
    Abstract: An Ethernet device includes receive buffers and transmit buffers of a port, and a processor. The buffers are each associated with a respective class of service. The processor operates to determine a current buffer utilization in a receive buffer, determine that the current buffer utilization is different than a buffer threshold for the receive buffer, determine a data rate limit for the class of service associated with the receive buffer based upon the difference between the current buffer utilization and the buffer threshold, and send a data rate limit frame to another device coupled to the port. The data rate limit frame includes the data rate limit for the class of service.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Hendrich M. Hernandez, Gaurav Chawla, Robert L. Winter
  • Patent number: 9367411
    Abstract: A device includes a first processing unit and a second processing unit. The first processing unit is configured to execute a performance test on the device. The second processing unit is in communication with the first processing unit, and is configured to migrate an application from the second processing unit to the first processing unit. The second processing unit is further configured to detect a failure of the first processing unit, to migrate the application to a third processing unit in response to the failure of the first processing unit, and to assign a first plurality of ports to the third processing unit in response to the failure of the first processing unit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: June 14, 2016
    Assignee: DELL PRODUCTS, LP
    Inventors: Saikrishna Kotha, Dean W. Peters, Gaurav Chawla
  • Patent number: 9325087
    Abstract: A clip-type connector for electrically coupling a substrate with a device or another substrate is disclosed. An electrical connector comprises a top plate and a bottom plate. An array of contacts are on at least one of the top plate and bottom plate. A hinge is located between the top plate and the bottom plate such that the hinge mechanically connects the top plate to the bottom plate. A spring applying a force against the top and bottom plates.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D. Heppner, Jeffory L Smalley, Vijaykumar Krithivasan
  • Publication number: 20160094461
    Abstract: An information handling system (IHS) network includes a switch IHS that coupled together a plurality of server IHSs. A source software-defined (SD) virtual appliance is located on one of the plurality of server IHSs. A destination SD virtual appliance is located on one of the plurality of server IHSs. An SD network controller is located on at least one of the plurality of server IHSs. The SD network controller is configured to receive a data traffic flow identifier and policy information that is associated with at least one data traffic flow policy from the source SD virtual appliance. The SD network controller determines a plurality of ports located between the source SD virtual appliance and the destination SD virtual appliance using the data traffic flow identifier. The SD network controller then configures each of the plurality of ports using the at least one data traffic flow policy.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Sudhir Vittal Shetty, Gaurav Chawla, Joseph L. White
  • Patent number: 9300590
    Abstract: An Ethernet device includes receive buffers and transmit buffers of a port, and a processor. The buffers are each associated with a respective class of service. The processor operates to determine a current buffer utilization in a receive buffer, determine that the current buffer utilization is different than a buffer threshold for the receive buffer, determine a data rate limit for the class of service associated with the receive buffer based upon the difference between the current buffer utilization and the buffer threshold, and send a data rate limit frame to another device coupled to the port. The data rate limit frame includes the data rate limit for the class of service.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 29, 2016
    Assignee: DELL PRODUCTS, LP
    Inventors: Hendrich M. Hernandez, Gaurav Chawla, Robert L. Winter
  • Publication number: 20160079150
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan
  • Patent number: 9288120
    Abstract: A Data Center Bridged (DCB) Information Handling System (IHS) network include a plurality of switch IHSs that are connected together to provide the IHS network, and a management IHS coupled to each of the plurality of switch IHSs through a management network. The management IHS is configured to identify a plurality of data traffic flows and, for each identified data traffic flow, to determine a flow path through the IHS network. The flow paths include at least some of the plurality of switch IHSs, and the management IHS provides configuration information to each of the switch IHSs included in a flow path such that a quality of service (QoS) is provided for the data traffic flow along that flow path through the DCB IHS network according to the configuration information. Thus, the systems and methods utilize flow based networking to configure and manage DCB IHS networks.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: Dell Products L.P.
    Inventors: Gaurav Chawla, Rajesh Narayanan, Shyamkumar T. Iyer
  • Patent number: 9262197
    Abstract: Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 16, 2016
    Assignee: Dell Products L.P.
    Inventors: Gaurav Chawla, Robert Wayne Hormuth, Shyamkumar T. Iyer, Duk M. Kim