Abstract: A method and an apparatus are provided in which an analog signal may be sampled by an analog-to-digital converter (ADC) to generate digital signal samples affected by baseline wander. Digital signal processing (DSP) may be performed on the digital signal samples to generate a recovered signal with corrected baseline wander. The DSP is performed using a first adaptable coefficient for a current digital signal sample and a second adaptable coefficient for a previous digital signal sample.

Abstract: A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1?M?Z, determining an ErrorM using the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the ErrorM. The adjusting of the input voltage may include generating a modified voltage Vd, wherein Vd=A*Vin+B, and each of A and B is determined using ?M sign(Errorm).

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

Abstract: A system and method for configuring a serial receiver. In some embodiments, the method, includes: setting a threshold of a data slicer to a first threshold value; receiving, by the data slicer, a first data value; and setting the threshold of the data slicer to a second threshold value, the second threshold value being equal to the first threshold value plus a first adjustment, the first adjustment having the same sign as the first data value minus the first threshold value.

Abstract: A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

Abstract: A system and method for setting one or more compensation coefficients for a transistor. In some embodiments, a method for setting a first compensation coefficient for a transistor includes: determining a plurality of measured transistor currents, each at a respective one of a plurality of transistor control voltages; setting the first compensation coefficient based on the measured transistor currents and the transistor control voltages; and adjusting a voltage applied to a gate of the transistor based on the first compensation coefficient, the voltage corresponding to a color value.

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: A method of compensating for change in pixel and a display device incorporating such method are presented. The method includes dividing pixels into groups including a previous group L?1, a current group L and a next group L+1; determining Aconverged[L] and Bconverged[L] for each pixel in the current group L; for each pixel in the current group L, determining a first moving average Amean[L] and a second moving average Bmean[L] as follows: A mean [ L ] = A ? mean [ L - 1 ] ? ( K - 1 ) + A [ L ] K , B mean [ L ] = B ? mean [ L - 1 ] ? ( K - 1 ) + B [ L ] K , wherein Amean[L?1] is a first moving average of a pixel in the corresponding column in the previous group L?1, Bmean[L?1] is a second moving average of a pixel in the corresponding column in the previous group L?1, and K is a moving average window; and for the next group L+1, setting a first initial value A0[L+1] and a second initial value A0[L+1] of each pixel to Amean[L] and Bmean[L].

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: Systems and methods relate to auto-tagging of data in a data lake or a data storage. Generating a statistical summary of the data lake and interactively receiving data in a selected column of an exemplar data addresses an issue of efficiently and accurately auto-tagging data in a data lake. The present disclosure automatically generates a statistical summary of the data lake using a lightweight off-line processing. A graphical user interface interactively receives an exemplar data file with a selection of a column in the exemplar data file. A list of candidate data-tagging patterns is generated based on the statistical summary and updates the list by removing candidate data-tagging patterns that under-generalize the data. The present disclosure determines a data-tagging pattern by selecting a candidate data-tagging profile from the list based on having the least number of matching columns in the data lake.

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: Systems and methods relate to auto-tagging of data in a data lake or a data storage. Generating a statistical summary of the data lake and interactively receiving data in a selected column of an exemplar data addresses an issue of efficiently and accurately auto-tagging data in a data lake. The present disclosure automatically generates a statistical summary of the data lake using a lightweight off-line processing. A graphical user interface interactively receives an exemplar data file with a selection of a column in the exemplar data file. A list of candidate data-tagging patterns is generated based on the statistical summary and updates the list by removing candidate data-tagging patterns that under-generalize the data. The present disclosure determines a data-tagging pattern by selecting a candidate data-tagging profile from the list based on having the least number of matching columns in the data lake.

Abstract: Systems and methods relate to auto-tagging of data in a data lake or a data storage. Generating a statistical summary of the data lake and interactively receiving data in a selected column of an exemplar data addresses an issue of efficiently and accurately auto-tagging data in a data lake. The present disclosure automatically generates a statistical summary of the data lake using a lightweight off-line processing. A graphical user interface interactively receives an exemplar data file with a selection of a column in the exemplar data file. A list of candidate data-tagging patterns is generated based on the statistical summary and updates the list by removing candidate data-tagging patterns that under-generalize the data. The present disclosure determines a data-tagging pattern by selecting a candidate data-tagging profile from the list based on having the least number of matching columns in the data lake.

Abstract: A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1?M?Z, determining an ErrorM using the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the ErrorM. The adjusting of the input voltage may include generating a modified voltage Vd, wherein Vd=A*Vin+B, and each of A and B is determined using ?M sign(Errorm).

Abstract: A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.

Abstract: A system and method for setting one or more compensation coefficients for a transistor. In some embodiments, a method for setting a first compensation coefficient for a transistor includes: determining a plurality of measured transistor currents, each at a respective one of a plurality of transistor control voltages; setting the first compensation coefficient based on the measured transistor currents and the transistor control voltages; and adjusting a voltage applied to a gate of the transistor based on the first compensation coefficient, the voltage corresponding to a color value.

Abstract: A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

Abstract: A method for compensating for characteristics of a transistor. In some embodiments, the method includes: measuring an error value, the error value being a difference between: a target current and a current driven by the transistor when the transistor is controlled by a compensated control signal based on an input control signal; adding to a first compensation parameter a first adjustment; adding to a second compensation parameter a second adjustment; and applying to a gate of the transistor a voltage equal to the sum of: the second compensation parameter, and the product of: the first compensation parameter, and an uncompensated drive voltage.

Abstract: A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.