Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Abstract: An adder with first and second majority gates is provided. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.