Patents by Inventor Gaurav Thareja

Gaurav Thareja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203490
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 25, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Publication number: 20200135464
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a non-perpendicular angle to the plane of the surface to selectively deposit the material on a top portion of one or more features on the substrate and form an overhang extending beyond a first sidewall of the one or more features; and etching a first layer of the substrate beneath the one or more features selective to the deposited material.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: SREE RANGASAI V. KESAPRAGADA, JONATHAN R. BAKKE, JOUNG JOO LEE, BENCHERKI MEBARKI, CHRISTOPHER NGAI, REGINA FREED, GAURAV THAREJA, TEJINDER SINGH, JORGE PABLO FERNANDEZ
  • Publication number: 20200091010
    Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 19, 2020
    Inventors: Xuebin LI, Schubert S. CHU, Errol Antonio C. SANCHEZ, Patricia M. LIU, Gaurav THAREJA, Raymond HUNG
  • Publication number: 20190385851
    Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 19, 2019
    Inventors: SRINIVAS GANDIKOTA, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
  • Patent number: 10410867
    Abstract: An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second contact that correspond to a transistor and are on a second fin; an interlayer dielectric (ILD) collinear with and between the first and second contacts; wherein (a) the first and second gates are collinear and the first and second contacts are collinear; (b) the ILD includes a recess that comprises a cap layer including at least one of an oxide and a nitride. Other embodiments are described herein.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Vyom Sharma, Rohan K. Bambery, Christopher P. Auth, Szuya S. Liao, Gaurav Thareja
  • Publication number: 20190252239
    Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 15, 2019
    Applicant: Applied Materials, Inc.
    Inventors: Ashish Pal, Gaurav Thareja, San Kuei Lin, Ching-Mei Hsu, Nitin K. Ingle, Ajay Bhatnagar
  • Publication number: 20180315607
    Abstract: An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second contact that correspond to a transistor and are on a second fin; an interlayer dielectric (ILD) collinear with and between the first and second contacts; wherein (a) the first and second gates are collinear and the first and second contacts are collinear; (b) the ILD includes a recess that comprises a cap layer including at least one of an oxide and a nitride. Other embodiments are described herein.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Vyom Sharma, Rohan K. Bambery, Christopher P. Auth, Szuya S. Liao, Gaurav Thareja
  • Publication number: 20180019170
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Application
    Filed: August 3, 2017
    Publication date: January 18, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, DANIEL B. AUBERTINE, ANAND S. MURTHY, GAURAV THAREJA, TAHIR GHANI
  • Patent number: 9728464
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Publication number: 20150115216
    Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 30, 2015
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
  • Patent number: 8957476
    Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
  • Publication number: 20140175543
    Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
  • Publication number: 20140027860
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani