Patents by Inventor Gayle W. Miller
Gayle W. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8378414Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.Type: GrantFiled: June 30, 2011Date of Patent: February 19, 2013Assignee: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
-
Patent number: 8138578Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.Type: GrantFiled: April 20, 2009Date of Patent: March 20, 2012Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
-
Publication number: 20110260250Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.Type: ApplicationFiled: June 30, 2011Publication date: October 27, 2011Applicant: ATMEL CORPORATIONInventors: Gayle W. Miller, Volker Dudek, Michael Graf
-
Patent number: 7848070Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: July 21, 2008Date of Patent: December 7, 2010Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
-
Patent number: 7642181Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.Type: GrantFiled: January 30, 2006Date of Patent: January 5, 2010Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Irwin D. Rathbun, Bryan D. Sendelweck, Thomas S. Moss, III
-
Patent number: 7629649Abstract: Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.Type: GrantFiled: May 9, 2006Date of Patent: December 8, 2009Assignee: Atmel CorporationInventors: Gayle W. Miller, Thomas S. Moss, Mark A. Good
-
Publication number: 20090206452Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.Type: ApplicationFiled: April 20, 2009Publication date: August 20, 2009Applicant: Atmel CorporationInventors: Gayle W. Miller, JR., Bryan D. Sendelweck
-
Patent number: 7541250Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.Type: GrantFiled: March 7, 2006Date of Patent: June 2, 2009Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
-
Patent number: 7521312Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.Type: GrantFiled: January 5, 2007Date of Patent: April 21, 2009Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
-
Publication number: 20080290426Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.Type: ApplicationFiled: August 4, 2008Publication date: November 27, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
-
Publication number: 20080278874Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: ApplicationFiled: July 21, 2008Publication date: November 13, 2008Inventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, JR., Irwin Rathbun, Peter Grombach, Manfred Klaussner
-
Publication number: 20080201088Abstract: A system and method for monitoring a process. The system includes a processing chamber for receiving a workpiece, a processor coupled to the processing chamber, and at least one surface acoustic wave (SAW) device coupled to the workpiece, and wherein the processor utilizes the at least one SAW device to determine the conditions of the workpiece during processing. According to the method and system disclosed herein, the present invention provides inexpensive, accurate, and abundant information to control a process.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicant: Atmel CorporationInventor: Gayle W. Miller
-
Patent number: 7407851Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.Type: GrantFiled: March 22, 2006Date of Patent: August 5, 2008Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
-
Publication number: 20080173940Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
-
Patent number: 7402846Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: October 20, 2005Date of Patent: July 22, 2008Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
-
Publication number: 20080166862Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Inventors: Gayle W. Miller, Bryan D. Sendelweck
-
Publication number: 20080135933Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: ApplicationFiled: January 23, 2008Publication date: June 12, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
-
Publication number: 20080108212Abstract: Apparatus and a method for adding non-volatile memory cells with trench-filled vertical gates to conventional MOSFET surface devices that have their drain and source regions horizontally positioned near the top surface of a substrate. A surface MOSFET device is used as a structural platform to which is added a vertical trench-filled polysilicon gate and a word line region using a small number of additional mask layers and fabrication process modifications. A vertical trench filled polysilicon gate is formed in a deep trench in a lower region of the substrate and adjacent to a MOSFET body portion of the substrate. The vertical trench-filled polysilicon gate in the deep trench is isolated by dielectric material from the body portion of the MOSFET and from a word line region that is formed in the lower region of the substrate.Type: ApplicationFiled: October 19, 2006Publication date: May 8, 2008Applicant: ATMEL CORPORATIONInventors: Thomas S. Moss, Lee A. Bowman, Gayle W. Miller, Stefan Schwantes
-
Patent number: 7348256Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: GrantFiled: July 25, 2005Date of Patent: March 25, 2008Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Volker Dudek, Michael Graf
-
Patent number: 7230342Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.Type: GrantFiled: August 31, 2005Date of Patent: June 12, 2007Assignee: Atmel CorporationInventors: Franz Dietz, Volker Dudek, Michael Graf, Stefan Schwantes, Gayle W. Miller, Jr.