Patents by Inventor Gayle W. Miller
Gayle W. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6277707Abstract: A method of forming a semiconductor device on a substrate including the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.Type: GrantFiled: December 16, 1998Date of Patent: August 21, 2001Assignee: LSI Logic CorporationInventors: Brian R. Lee, Gayle W. Miller, Kunal N. Taravade
-
Patent number: 6268224Abstract: A method of fabricating a semiconductor wafer having a polishing endpoint layer which is formed by implanting ions into the wafer includes the step of polishing the wafer in order to remove material from the wafer. The method also includes the step of detecting a first change in friction when material of the ion-implanted polishing endpoint layer begins to be removed during the polishing step. The method further includes the step of detecting a second change in friction when material of the ion-implanted polishing endpoint layer ceases to be removed during the polishing step. Moreover, the method includes the step of terminating the polishing step in response to detection of the second change in friction. An apparatus for polishing a semiconductor wafer down to an ion-implanted polishing endpoint layer in the wafer is also disclosed.Type: GrantFiled: June 30, 1998Date of Patent: July 31, 2001Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Michael F. Chisholm
-
Patent number: 6258205Abstract: An apparatus for planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is disclosed. The apparatus is operable to detect the endpoint based upon the chemical slurry whether a catalytic reaction has occurred due to the polishing platen removing a portion of the catalyst material from the wafer.Type: GrantFiled: March 24, 2000Date of Patent: July 10, 2001Assignee: LSI Logic CorporationInventors: Brynne K. Chisholm, Gayle W. Miller, Gail D. Shelton
-
Patent number: 6208029Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: March 31, 1997Date of Patent: March 27, 2001Assignee: Hyundai Electronics AmericaInventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
-
Patent number: 6206573Abstract: The present invention provides bearing assemblies and methods of manufacturing bearing assemblies which allow for reliable, non-intrusive wear detection. In one embodiment, a bearing assembly (10) includes first and second bearing members (12, 14) adapted for movement relative to each other. The first bearing member includes an outer layer (24) that is adapted to wear in response to the relative movement between bearing members, and an inner layer. The inner layer includes a base portion (28) having a first hardness and a plurality of spaced apart wear indicating regions (30) having a second hardness, whereby the first hardness and second hardness are different. The wear indicating regions are adapted to produce a vibration after sufficient wear of the outer layer.Type: GrantFiled: May 21, 1998Date of Patent: March 27, 2001Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Gail D. Shelton
-
Patent number: 6150175Abstract: Radio frequency photo conductive decay is used to monitor a small piece of high-grade silicon to determine if copper contamination has been removed from a probe tool. A probe tool is placed in contact with a small "waferette" of silicon repeatedly until the copper signal is diminished, indicating that the tool may be used for other products without concern for copper contamination.Type: GrantFiled: December 15, 1998Date of Patent: November 21, 2000Assignee: LSI Logic CorporationInventors: Gail D. Shelton, Gayle W. Miller
-
Patent number: 6136719Abstract: A method of fabricating a semiconductor wafer is disclosed.Type: GrantFiled: April 30, 1999Date of Patent: October 24, 2000Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Gail D. Shelton
-
Patent number: 6130117Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.Type: GrantFiled: May 19, 1998Date of Patent: October 10, 2000Assignee: LSI Logic CorporationInventors: John D. Walker, Todd A. Randazzo, Gayle W. Miller
-
Patent number: 6117779Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.Type: GrantFiled: December 15, 1998Date of Patent: September 12, 2000Assignee: LSI Logic CorporationInventors: Gail D. Shelton, Gayle W. Miller
-
Patent number: 6090724Abstract: A method for composing a low dielectric thermally conductive thin film is disclosed. A layer of precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried and becomes a layer of porous silica film. Subsequently, the silicon substrate is exposed to a methane gas atmosphere at a temperature of approximately 200-350.degree. C., during which methane gas molecules are oxidized locally to liberate carbon atoms. Some of the liberated carbon atoms will bond to the interior of the porous silica film. The carbon atoms from the methane gas molecules then permeate the nanopores within the porous silica film such that the entire nanostructure of the porous silica film is carbidized. As a result, a composite porous silica film, which may serve as a dielectric layer within an interconnect structure, is formed.Type: GrantFiled: December 15, 1998Date of Patent: July 18, 2000Assignee: LSI Logic CorporationInventors: Gail D. Shelton, Gayle W. Miller
-
Patent number: 6080670Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a sulfur-containing reporting specie includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method also includes the step of detecting presence of the sulfur-containing reporting specie in the material removed from the wafer. The method further includes the step of terminating the polishing step in response to detecting presence of the sulfur-containing reporting specie. A shallow trench isolation process for fabricating a semiconductor wafer is also disclosed.Type: GrantFiled: August 10, 1998Date of Patent: June 27, 2000Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Gail D. Shelton, Brynne K. Chisholm
-
Patent number: 6071818Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is discloes. One step of the method includes polishing a first side of the wafer in order to remove material from the wafer. Another step of the method includes determining that a catalytic reaction has occurred due to the polishing step removing the catalyst material of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the catalytic reaction has occurred. A polishing system is also disclosed which detects a polishing endpoint based upon a catalytic reaction triggered by a catalyst material of a polishing endpoint layer of a semiconductor device.Type: GrantFiled: June 30, 1998Date of Patent: June 6, 2000Assignee: LSI Logic CorporationInventors: Brynne K. Chisholm, Gayle W. Miller, Gail D. Shelton
-
Patent number: 6057571Abstract: A linear capacitor formed in an IC which has horizontally oriented interconnect layers that are vertically separated by dielectric material. Two separated metal plates of the capacitor are electrically connected to the conductors of different vertically-separated metal interconnect layers. The metal plates extend substantially vertically through the thicker dielectric material separating the interconnect layers, to provide a relatively high capacitance per unit of surface consumed. The interconnect layers to which the plates are connected are separated from a substrate of the IC by at least one layer of dielectric, to reduce parasitic effects. Forming the capacitor plates and the interconnect layers from at least some of the same metals simplifies construction and reduces cost, while providing linear response characteristics. Placing the capacitor between the interconnect layers avoids consuming space on the substrate to construct the capacitor.Type: GrantFiled: March 31, 1998Date of Patent: May 2, 2000Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Kenneth P. Fuchs
-
Patent number: 5963825Abstract: A fusible link and method for its fabrication. A polysilicon pad is formed on top of an insulating layer and covered with a second insulating layer. A trench is selectively etched into the second insulating layer exposing the top of the polysilicon pad. An fusible aluminum link is then formed over the second insulating layer and trench and conformal therewith. When a programming current is driven through the link, the aluminum melts and is absorbed by the polysilicon pad, thereby preventing the link's growback.Type: GrantFiled: August 26, 1992Date of Patent: October 5, 1999Assignee: Hyundai Electronics AmericaInventors: Steven S. Lee, Gayle W. Miller
-
Patent number: 5821572Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.Type: GrantFiled: December 17, 1996Date of Patent: October 13, 1998Assignee: Symbios, Inc.Inventors: John D. Walker, Todd A. Randazzo, Gayle W. Miller
-
Patent number: 5821013Abstract: A method and apparatus for forming layers of photo-sensitive materials in different thicknesses. A mask including a first area that substantially blocks light transmission and a second area having optical characteristics, which partially blocks light transmission is employed. Light is projected through the mask onto a layer of photo-sensitive material. The first area substantially blocks the light from passing through and leaves portions of the photo-sensitive material unexposed. The secondary area reduces the intensity of light passing through the mask and projected onto other portions of the photo-sensitive material. After developing the photo-sensitive material, at least two thicknesses of photo-sensitive material results. The second area may include a number of sections that vary from each other in optical characteristics such that the intensity of the light projected onto the layer of photo-sensitive material through the second area varies in steps or continuously.Type: GrantFiled: December 13, 1996Date of Patent: October 13, 1998Assignee: Symbios, Inc.Inventors: Gayle W. Miller, Brian R. Lee
-
Patent number: 5672905Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.Type: GrantFiled: August 26, 1992Date of Patent: September 30, 1997Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.Inventors: Steven S. Lee, Gayle W. Miller
-
Patent number: 5581861Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.Type: GrantFiled: June 2, 1995Date of Patent: December 10, 1996Assignees: AT&T Global Information Solutions Company, Hyundai Electronics, America & Symbios Logic Inc.Inventors: Steven S. Lee, Gayle W. Miller
-
Patent number: 5543361Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.Type: GrantFiled: December 8, 1994Date of Patent: August 6, 1996Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.Inventors: Steven S. Lee, Kenneth P. Fuchs, Gayle W. Miller
-
Patent number: 5459501Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.Type: GrantFiled: February 1, 1993Date of Patent: October 17, 1995Assignees: AT&T Global Information Solutions Company, Hyundai Electronics AmericaInventors: Steven S. Lee, Gayle W. Miller