Abstract: The disclosed technology relates to a complementary metal-oxide-semiconductor (CMOS) field effect device comprising a substrate; a first n-doped S/D region and a second n-doped S/D region; a first p-doped S/D region and a second p-doped S/D region; a first channel layer arranged above the substrate, the first channel layer comprising: a first sub-layer and a second sub-layer; wherein the first and second n-doped S/D regions are arranged at a first lateral side of the first channel layer, and the first and second p-doped S/D regions are arranged at a second lateral side of the first channel layer, the second lateral side being opposite to the first lateral side; wherein a conduction band edge of the first sub-layer has an energy below a conduction band edge of the second sub-layer; and wherein a valence band edge of the first sub-layer has an energy below a valence band edge of the second sub-layer; and a gate structure formed over one or more surfaces of the first and second sub-layers of the first channel la

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

Abstract: There is provided a method for forming a semiconductor device. The method comprising performing frontside processing comprising forming a transistor structure on a frontside of a substrate, the transistor structure comprising a first source/drain body and a second source/drain body located in a first and a second source/drain region, respectively, and a channel structure between the first source/drain body and the second source/drain body, wherein the first source/drain body and the second source/drain body have a first doping concentration. The method also includes, subsequent to the frontside processing, performing backside processing comprising exposing the first source/drain body from a backside of the substrate, and processing the first source/drain body to form, in the first source/drain region, a replacement source/drain body having a second doping concentration different from the first doping concentration.

Abstract: A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

Abstract: A device and method for forming a vertical channel device is disclosed.

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.