Patents by Inventor Geert Eneman

Geert Eneman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190172913
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.
    Type: Application
    Filed: October 26, 2018
    Publication date: June 6, 2019
    Inventors: Hu Liang, Xiuju Zhou, Geert Eneman
  • Publication number: 20190081156
    Abstract: A device and method for forming a vertical channel device is disclosed.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 14, 2019
    Applicant: IMEC VZW
    Inventors: Anabela Veloso, Geert Eneman, Nadine Collaert, Erik Rosseel
  • Patent number: 9876080
    Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 23, 2018
    Assignee: IMEC VZW
    Inventors: Bernardette Kunert, Robert Langer, Geert Eneman
  • Patent number: 9698262
    Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 4, 2017
    Assignees: IMEC VZW, Globalfoundries Inc.
    Inventors: Bartlomiej Pawlak, Geert Eneman
  • Patent number: 9633891
    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 25, 2017
    Assignee: IMEC VZW
    Inventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
  • Publication number: 20170033183
    Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.
    Type: Application
    Filed: July 25, 2016
    Publication date: February 2, 2017
    Applicant: IMEC VZW
    Inventors: Bernardette Kunert, Robert Langer, Geert Eneman
  • Publication number: 20160276478
    Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 22, 2016
    Inventors: Bartlomiej PAWLAK, Geert ENEMAN
  • Patent number: 9437681
    Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 6, 2016
    Assignees: IMEC VZW, Samsung Electronics Co. Ltd.
    Inventors: Seung Hun Lee, Geert Eneman
  • Patent number: 9406777
    Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 2, 2016
    Assignees: IMEC VZW, Samsung Electronics Co. Ltd.
    Inventors: Seung Hun Lee, Geert Eneman
  • Patent number: 9368498
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 14, 2016
    Assignee: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Publication number: 20160126131
    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 5, 2016
    Applicant: IMEC VZW
    Inventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
  • Patent number: 9257539
    Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: February 9, 2016
    Assignee: IMEC VZW
    Inventors: Rita Rooyackers, Nadine Collaert, Geert Eneman
  • Publication number: 20160027876
    Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.
    Type: Application
    Filed: May 12, 2015
    Publication date: January 28, 2016
    Applicants: SAMSUNG ELECTRONICS CO. LTD., IMEC VZW
    Inventors: Seung Hun Lee, Geert Eneman
  • Publication number: 20160027777
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Applicant: IMEC VZW
    Inventors: Geert ENEMAN, Benjamin VINCENT, Voon Yew THEAN
  • Patent number: 9171904
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 27, 2015
    Assignee: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Patent number: 9117777
    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 25, 2015
    Assignee: IMEC
    Inventors: Benjamin Vincent, Geert Eneman
  • Publication number: 20150179755
    Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 25, 2015
    Inventors: Rita Rooyackers, Nadine Collaert, Geert Eneman
  • Patent number: 9064702
    Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: June 23, 2015
    Assignees: IMEC, GLOBALFOUNDRIES INC.
    Inventors: David Brunco, Geert Eneman
  • Patent number: 9006705
    Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: April 14, 2015
    Assignees: IMEC, GLOBALFOUNDRIES Inc.
    Inventors: Geert Eneman, David Brunco, Geert Hellings
  • Publication number: 20140170837
    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: IMEC
    Inventors: Benjamin Vincent, Geert Eneman