Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.