Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

Abstract: A method is provided for forming a FET device.

Abstract: An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.

Abstract: A sensor is provided, the sensor including a field effect transistor comprising: (a) an active region comprising: (i) a source region and a drain region defining a source-drain axis and (ii) a channel region between the source region and the drain region; (b) a dielectric region on the channel region, comprising at least a first zone on a first portion of the channel region and a second zone on a second portion of the channel region, the first zone measuring from 1 to 100 nm in the direction of the source-drain axis and being adapted to create a different threshold voltage for the first portion of the channel region than for the second portion of the channel region, and (c) a fluidic gate region to which a top surface of the dielectric region is exposed. A biosensing device comprising such a sensor, a method for using such a sensor, and a process for making such a sensor are also provided.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

Abstract: A sensor is provided, the sensor including a field effect transistor comprising: (a) an active region comprising: (i) a source region and a drain region defining a source-drain axis and (ii) a channel region between the source region and the drain region; (b) a dielectric region on the channel region, comprising at least a first zone on a first portion of the channel region and a second zone on a second portion of the channel region, the first zone measuring from 1 to 100 nm in the direction of the source-drain axis and being adapted to create a different threshold voltage for the first portion of the channel region than for the second portion of the channel region, and (c) a fluidic gate region to which a top surface of the dielectric region is exposed. A biosensing device comprising such a sensor, a method for using such a sensor, and a process for making such a sensor are also provided.

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer.

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer.

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer.

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.

Abstract: An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.