Abstract: In an example embodiment there is provides method comprising obtaining a functional description of the integrated circuit, and generating, based on the functional description, a layout of the integrated circuit. Generating the layout comprises placing first and second cells of a standard cell library in the layout. The first and second cells are placed in the first and second cell rows, respectively, such that: the first cell edge of the first cell aligns with a first row boundary, the first cell edge of the second cell aligns with a second row boundary, and the second cell edges of the first and second cells align with and abut each other along a third row boundary between the first and second cell rows. The placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.

Abstract: A semiconductor device is provided. In one aspect, the device includes a first and second power rail structure extending in parallel, each including a bottom power rail and a top power rail arranged above the bottom power rail; a first and second row of complementary field-effect transistor (CFET) devices extending in parallel to the first and second power rail structures; a row of local interconnects arranged between and extending in parallel to the first and second row of CFET devices; and a logic cell. The first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects. The logic cell includes at least one CFET device of the first row of CFET devices configured to implement a first logic gate, and at least one CFET device of the second row of CFET devices configured to implement a second logic gate.

Abstract: A method is provided for forming a FET device.

Abstract: The disclosed technology relates to a complementary metal-oxide-semiconductor (CMOS) field effect device comprising a substrate; a first n-doped S/D region and a second n-doped S/D region; a first p-doped S/D region and a second p-doped S/D region; a first channel layer arranged above the substrate, the first channel layer comprising: a first sub-layer and a second sub-layer; wherein the first and second n-doped S/D regions are arranged at a first lateral side of the first channel layer, and the first and second p-doped S/D regions are arranged at a second lateral side of the first channel layer, the second lateral side being opposite to the first lateral side; wherein a conduction band edge of the first sub-layer has an energy below a conduction band edge of the second sub-layer; and wherein a valence band edge of the first sub-layer has an energy below a valence band edge of the second sub-layer; and a gate structure formed over one or more surfaces of the first and second sub-layers of the first channel la

Abstract: The present disclosure relates to a 3D IC, including a stack of device tiers comprising a first and a second device tier; a data processing circuit comprising a set of launch and capture circuits, and a set of processing stages, wherein each processing circuit is connected between a launch circuit and a capture circuit, and wherein the data processing circuit is partitioned between the first and second device tiers such that the set of launch and capture circuits is arranged in the first device tier and the set of processing stages is arranged in the second device tier.

Abstract: The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

Abstract: The disclosure relates to a complementary field effect transistor (CFET) structure. The CFET structure comprises: a vertical wall structure; a first transistor structure comprising one or more first channel layers; and a second transistor structure comprising one or more second channel layers, wherein the second transistor structure is stacked on the first transistor structure; wherein the first and the second transistor structure are arranged on one side of the vertical wall structure, and wherein the first and the second channel layers are in contact with a side surface of the vertical wall structure. The vertical wall structure comprises: a conductive core layer and a spacer layer which partially covers the conductive core layer on the side surface of the vertical wall structure, wherein the spacer layer has at least one opening to electrically connect the second transistor structure with the conductive core layer.

Abstract: A SRAM device includes a plurality of rows of transistor structures. Each row has top and bottom transistor structures. The device includes bit cells. Each bit cell includes first and second half cells. The half cells are arranged in a plurality of cell rows having transistor structures. Each half cell comprises an inverter and a pass gate. A plurality of power rail structures are interleaved with the rows of transistor structures such that a respective pair of neighboring first and second cell rows including a respective pair of neighboring first and second rows of transistor structures is arranged between a pair of consecutive power rail structures. Each power rail structure comprises a bottom power rail and a top power rail stacked over the bottom power rail, and bottom and top transistor structures of each inverter are coupled to the bottom and top power rails of the neighboring power rail structure.

Abstract: The disclosed technology relates to dynamic random access memory (DRAM) devices. The disclosed technology provides an integrated DRAM device including a DRAM and a logic circuit configured to control the DRAM. In one aspect, a DRAM device includes a plurality of stacked transistors arranged in a first region of the DRAM device, the stacked transistors being disposed one over another along a stacking direction, and a storage capacitor arranged in a second region of the DRAM device. The first region is positioned above the second region along the stacking direction. One of the plurality of stacked transistors is connected to the storage capacitor to form a DRAM cell of the DRAM, and remaining one or ones of the plurality of stacked transistors forms at least a portion of the logic circuit.

Abstract: A method for forming an integrated circuit device, the method comprising: forming a stack of field effect transistors, FETs, comprising a bottom FET and a top FET; forming a first trench underneath the bottom FET; forming a first hole, between the first trench and a first source/drain region of the bottom FET; forming a second hole, between the first hole and a contact of a contact layer arranged above the top FET; performing a first metal deposition to fill the first hole; the second hole; and part of the first trench, with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer below the recessed metal; performing a second metal deposition to fill the first trench with metal, thereby forming a first backside wiring line in the first trench.

Abstract: The disclosed technology relates to a ferroelectric memory device configured for non-destructive readout. The non-destructive readout is carried out by applying a voltage to the ferroelectric capacitor's plates via voltage lines and sensing the charge output through one of the voltage lines over four sensing phases. The voltage value changes symmetrically across these phases. A charge sensor detects the resulting charge, summing it with opposite signs for the first and third phases versus the second and fourth phases.

Abstract: In an aspect there is provided a semiconductor device including: first and second parallel multilayered active regions, each including at least one lower semiconductor layer and at least one upper semiconductor layer stacked over the at least one lower semiconductor layer; and a PIN diode structure including: an epitaxial first lower semiconductor body arranged along a first portion of the first active region, at a level of the at least one lower semiconductor layer of the first active region, and an epitaxial second lower semiconductor body arranged along a second portion of the second active region directly opposite to the first portion, at a level of the at least one lower semiconductor layer of the second active region; an epitaxial first upper semiconductor body arranged along the first portion, at a level of the at least one upper semiconductor layer of the first active region and spaced apart from the first lower semiconductor body, and an epitaxial second upper semiconductor body arranged along the se

Abstract: A method and a semiconductor device are provided. An example method may include forming a stack of field effect transistors, FETs, on top of a substrate. The method may also include forming a first insulating layer laterally surrounding the stack of FETs and etching a hole into the first insulating layer, the hole extending between a top endpoint and a bottom endpoint. The method may further include filling the hole with electrically conductive material such that the electrically conductive material of the filled hole forms a via. Moreover, the method may include etching, from a bottom side of the substrate towards the first insulating layer, a trench, a top part of the trench comprising both a bottom side of the first source/drain region and the bottom endpoint. The method may also include filling the top part of the trench with electrically conductive material.

Abstract: A fin-shaped structure formed on a base substrate that could comprise a stack of alternating sacrificial layers and semiconductor layers. The stack materials could be removed relative to the dummy gates and relative to a mask formed before or after the dummy gates, creating lateral recesses with U-shaped sidewalls formed of stacked U-shaped portions of the sacrificial and semiconductor layers. Semiconductor material could be grown in the recesses by epitaxial growth, starting from the U-shaped semiconductor portions. The grown material could be lattice mismatched relative to the material of the U-shaped portions. No dislocations could be created due to oppositely interfering growth fronts, and a desired stress can thereby be created in at least one or more channel sheets of the eventual transistors. These transistors can be arranged in a forksheet configuration, after producing a trench to remove the mask, and filling the trench by a dielectric material.

Abstract: The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure which is arranged above the first transistor structure and which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure of the at least one CFET element, and a power routing line arranged above the second transistor structure of the at least one CFET element. The power routing line is electrically connected to the source and/or drain structure of the second transistor structure from the top. The at least one CFET element further has a tap connection structure which is arranged to electrically connect the power rail with the source and/or drain structure of the second transistor structure. The tap connection structure is arranged to bypass the first transistor structure on one side.

Abstract: An integrated circuit device includes a clock distribution network that includes a clock mesh formed by first clock lines and second clock lines. The first clock lines and the second clock lines are arranged at the same level in a backside interconnect structure of the integrated circuit device and are interconnected by crossing each other.

Abstract: Provided herein is a nanosheet device that includes a first and a second transistor structure, each comprising a respective source region, drain region, and channel region extending between the respective source and drain regions, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure includes a first set of vertically stacked channel layers, wherein each channel layer of the first set of vertically stacked channel layers has an inward facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure includes a second set of vertically stacked channel layers, and wherein each channel layer of the second set of vertically stacked channel layers has an inward facing surface contacting a second side surface, opposite to the first side surface, of the dielectric wall

Abstract: A nanostructure according to the present disclosure comprises a pair of nanosheet or nanowire transistors configured to conduct charge by carriers of opposite polarity (such as n and p type carriers), wherein one of the pair of transistors is provided with inner spacers and the other is not provided with inner spacers. Depending on the type of charge carrier, the omission of the inner spacers may improve the admittance of the device. This is demonstrated in an example embodiment comprising a Si-channel PMOS nanosheet transistor. Conversely, in a Si-channel NMOS nanosheet transistor, the omission of the inner spacers has a negative effect on the parasitic capacitance that outweighs some of the benefits of the inner spacer omission. An example embodiment of the present disclosure includes complementary NMOS and PMOS silicon transistors, wherein the NMOS is provided with inner spacers and the PMOS is not provided with inner spacers.

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

Abstract: A method is provided for forming a FET device.