Patents by Inventor Gen Pei
Gen Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373548Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.Type: GrantFiled: August 27, 2008Date of Patent: June 21, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Gen Pei, Scott D. Luning, Johannes van Meer
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Patent number: 9105650Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.Type: GrantFiled: February 21, 2014Date of Patent: August 11, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140170829Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140073106Abstract: A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8617957Abstract: A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.Type: GrantFiled: September 10, 2012Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Josephine B Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W Sleight
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Patent number: 8618636Abstract: A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.Type: GrantFiled: September 11, 2012Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Josephine B Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W Sleight
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Patent number: 8610181Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.Type: GrantFiled: September 21, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8603868Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.Type: GrantFiled: December 19, 2011Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20130153972Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.Type: ApplicationFiled: September 21, 2012Publication date: June 20, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL A. GUILLORN, GEN PEI LAUER, ISAAC LAUER, JEFFREY W. SLEIGHT
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Publication number: 20130153971Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.Type: ApplicationFiled: December 19, 2011Publication date: June 20, 2013Applicant: International Business Machines CorporationInventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8400854Abstract: The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.Type: GrantFiled: January 26, 2010Date of Patent: March 19, 2013Assignee: SanDisk Technologies Inc.Inventors: Gen Pei, Lanlan Gu, Nima Mokhlesi, Idan Alrod, Eran Sharon, Itshak Afriat
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Patent number: 8012820Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.Type: GrantFiled: March 21, 2011Date of Patent: September 6, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Amlan Majumdar, Gen Pei, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight
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Publication number: 20110165739Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.Type: ApplicationFiled: March 21, 2011Publication date: July 7, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Amlan Majumdar, Gen Pei, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight
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Patent number: 7943999Abstract: A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.Type: GrantFiled: September 10, 2008Date of Patent: May 17, 2011Assignee: Global Foundries Inc.Inventor: Gen Pei
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Publication number: 20110063918Abstract: The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.Type: ApplicationFiled: January 26, 2010Publication date: March 17, 2011Inventors: Gen Pei, Lanlan Gu, Nima Mokhlesi, Idan Alrod, Eran Sharon, Itshak Afriat
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Patent number: 7816767Abstract: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.Type: GrantFiled: February 10, 2009Date of Patent: October 19, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Gen Pei, Zoran Krivokapic
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Publication number: 20090289305Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.Type: ApplicationFiled: August 4, 2009Publication date: November 26, 2009Applicant: International Business Machines CorporationInventors: Amlan Majumdar, Gen Pei, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight
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Publication number: 20090242989Abstract: In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Inventors: KEVIN K. CHAN, Jack O. Chu, Jin-Ping Han, Thomas S. Kanarsky, Hung Y. Ng, Qiqing Quyang, Gen Pei, Chun-Yung Sung, Henry K. Utomo, Thomas A. Wallner
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Publication number: 20090146212Abstract: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.Type: ApplicationFiled: February 10, 2009Publication date: June 11, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Gen Pei, Zoran Krivokapic
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Patent number: 7508050Abstract: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.Type: GrantFiled: March 16, 2006Date of Patent: March 24, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Gen Pei, Zoran Krivokapic