Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing.

Abstract: A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing.

Abstract: A semiconductor transistor structure has a plurality of fins, a cap on the center portion of the top of each of the fins, a conductive liner lining the cap and the sidewalls of the center portion of the fins, and an insulator between the center portions of the fins. The insulator contacts the conductive liner, and the fins extend further from the surface of the substrate relative to an amount the insulator extends from the surface of the substrate. The structure further includes a conductive layer positioned on the insulator between the center portions of the fins and positioned between the cap of the fins. The conductive layer contacts the conductive liner.

Abstract: A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.

Abstract: A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.

Abstract: A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.

Abstract: A method of manufacturing a semiconductor device including implanting an element selected from fluorine and nitrogen, over the entire region of a semiconductor substrate; oxidizing the semiconductor substrate to thereby form a first oxide film over the surface of the semiconductor substrate; selectively removing the first oxide film in a partial region; oxidizing the semiconductor substrate in the partial region to thereby form a second oxide film thinner than the first oxide film in the partial region; and forming gates to thereby form transistors.

Abstract: A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.

Abstract: Provided is a semiconductor device including: a first n-channel fin-type field effect transistor formed on a first crystal plane; and a second n-channel fin-type field effect transistor formed on the first crystal plane and having a gate length longer than that of the first n-channel fin-type field effect transistor. A side surface of a fin of the first n-channel fin-type field effect transistor and a side surface of a fin of the second n-channel fin-type field effect transistor are both formed on a second crystal plane having a carrier mobility lower than that of the first crystal plane. The width of the fin of the second n-channel fin-type field effect transistor is greater than the width of the fin of the first n-channel fin-type field effect transistor.

Abstract: Provided is a semiconductor device which includes, on the same semiconductor substrate, a first FET and a second FET higher in threshold voltage than the first FET. The first FET includes a first gate insulating film and a first gate electrode. The second FET includes a second gate insulating film and a second gate electrode. The first gate electrode, the second gate insulating film, and the second gate electrode contain at least one metal element selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ta, and W. Concentration of the at least one metal element at an interface between the second gate insulating film and the second gate electrode in the second FET is higher than concentration of the at least one metal element at an interface between the first gate insulating film and the first gate electrode in the first FET.

Abstract: A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween.