Abstract: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base structure is then treated with an anisotropic annealing source inclined in the source-to-drain direction of the base structure relative to the normal of the substrate, such that one of the source and drain extensions is shadowed by the gate and the other is annealed more.

Abstract: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base structure is then treated with an anisotropic annealing source inclined in the source-to-drain direction of the base structure relative to the normal of the substrate, such that one of the source and drain extensions is shadowed by the gate and the other is annealed more.

Abstract: The application discloses caner-associated genes and their products, especially those identifiable by SEREX. The genes and products are used to identify, track and treat cancer. Preferably the cancer is a gastro-intestinal cancer.

Abstract: A polishing element comprising a polishing platen, a polishing sub-pad and a polishing pad is provided. The polishing sub-pad is set up over the polishing platen and the polishing pad is set up over the polishing sub-pad. A first surface of the polishing sub-pad interfaces with the polishing pad and a second surface of the polishing sub-pad interfaces with the platen. Either the first surface or the second surface of the polishing sub-pad is an undulating surface.

Abstract: A wafer polishing method is provided. A first polishing pad comprising a plurality of abrasive units is provided. A first polishing operation is performed on the first polishing pad to planarize a wafer. Thereafter, a second polishing pad comprising a plurality of abrasive units is provided. The surface of the abrasive unit in contact with the wafer is roughened. A second polishing operation is performed on the second polishing pad. Since a second polishing operation using a second polishing pad with a roughened surface is performed, gradual reduction of polishing rate as the polish layer is planarized can be avoided.