Polishing pad and method of polishing wafer
A wafer polishing method is provided. A first polishing pad comprising a plurality of abrasive units is provided. A first polishing operation is performed on the first polishing pad to planarize a wafer. Thereafter, a second polishing pad comprising a plurality of abrasive units is provided. The surface of the abrasive unit in contact with the wafer is roughened. A second polishing operation is performed on the second polishing pad. Since a second polishing operation using a second polishing pad with a roughened surface is performed, gradual reduction of polishing rate as the polish layer is planarized can be avoided.
1. Field of Invention
The present invention relates to a polishing pad and a method of polishing a wafer. More particularly, the present invention relates to a polishing pad and a wafer polishing method that can improve polishing efficiency.
2. Description of Related Art
In the fabrication of semiconductor devices, one way of increasing the level of integration in a memory wafer or a logic wafer is to increase the aspect ratio and the number of conductive circuit layers in a stack. However, as the number of stacked circuit layers in a multi-layered structure increases, undulation or warping of the surface of a chip frequently occurs. To remove such non-planarity from a wafer surface, special global planarization techniques are developed. When the special planarization technique is incorporated to the fabrication of semiconductor, a multi-layered stack with many conductive line layers can be produced with a relatively high yield. One of the earliest corporations using the global planarization techniques was IBM. The original method included performing a chemical-mechanical polishing (CMP) operation to form buried conductive lines in a damascene process. During the chemical-polishing operation, surface planarization is achieved through slurry of abrasive particles and relative motion between the surface of a wafer and a polishing pad with suitable elasticity and hardness.
However, dishing may occur when slurry with suspended abrasive particles is used in a chemical-mechanical polishing operation to remove dielectric material (for example, silicon oxide) on silicon nitride within the active region of a shallow trench isolation (STI) structure. Recently, a new type of chemical-mechanical polishing method requiring no slurry has been developed. The new polishing method is called ‘fixed abrasive chemical-mechanical polishing (FA-CMP)’. In the FA-CMP technique, the abrasive particles are fixed onto a superficial layer of a polishing pad. In other words, the polishing pad has a sand-paper-like surface that directly functions as a polisher. One major advantage of this method is a relatively high polishing selectivity between the dielectric material (for example, silicon oxide) and the silicon nitride. Furthermore, the method has high planarization efficiency but causes very little dishing in the silicon oxide within a shallow trench isolation (STI) structure.
As shown in
Thereafter, as shown in
Accordingly, the aforementioned fixed abrasive CMP technique has a low polishing rate and a reduced polishing efficiency when the surface to be polished is too smooth. Thus, the minimum thickness of a polished layer is often set to about 1000 Å. Yet, the width of a STI gap-fill process is severely limited when the feature line width is only about 90 nm or smaller. In other words, the fixed abrasive CMP technique will encounter severe restrictions if it is applied to produce the next generation of smaller size semiconductors. To be useful, the fixed abrasive chemical-mechanical technique must be improved so that a high polishing selectivity ratio can be maintained without causing dishing at the end of a polishing operation.
SUMMARY OF THE INVENTIONAccordingly, one object of the present invention is to provide a polishing pad capable of increasing the polishing rate of fixed abrasive chemical-mechanical polishing operation.
Another object of this invention is to provide a method for polishing a wafer capable of lifting the thickness restriction of the polished layer in the conventional method.
Still another object of this invention is to provide a method for polishing a wafer capable of increasing the width in a shallow trench isolation (STI) gap-fill process.
Still another object of this invention is to provide a method for polishing a wafer capable of roughening up the abrasive particles on a polishing pad in-situ while a wafer polishing operation is performed.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a polishing pad. The polishing pad has a plurality of abrasive units thereon. Each abrasive unit comprises a layer of adhesive compound and a plurality of abrasive particles such as cerium oxide (CeO2) evenly distributed within the adhesive layer. In addition, the surface of the abrasive unit in contact with the wafer is roughened.
This invention also provides a wafer polishing method. First, a first polishing pad is provided. The first polishing pad has a plurality of abrasive units each comprising a layer of adhesive compound having evenly distributed abrasive particles therein. The abrasive particles inside the adhesive layer are fabricated using cerium oxide (CeO2), for example. Thereafter, a first polishing operation is carried out to planarize the surface of a wafer above the first polishing pad. Next, a second polishing pad is provided. Similarly, the second polishing pad has a plurality of abrasive units each comprising a layer of adhesive compound having evenly distributed abrasive particles therein. The upper surface of each abrasive unit has a roughened surface and the abrasive particles inside the adhesive layer is fabricated using cerium oxide (CeO2), for example. Finally, a second polishing operation is carried out above the second polishing pad.
This invention also provides an alternative wafer polishing method. First, a wafer holder suitable for grasping a wafer is provided. The wafer holder has a retainer ring. The retainer ring has a grooves patterned into various shapes including crosses, concentric rings, spiral patterns or a combination of the aforementioned. Thereafter, a polishing pad is provided. The polishing pad has a plurality of abrasive units each comprising a layer of adhesive compound with evenly distributed abrasive particles therein. With the wafer gripped firmly by the wafer holder, the wafer holder is pressed onto the polishing pad to carry out a polishing operation. During the polishing operation, the groove patterns on the retainer ring is in contact with the surface of the abrasive units. Through the groove patterns, the surface of contact between the abrasive units and the wafer is roughened.
Accordingly, this invention utilizes the roughened surface of a polishing pad (the polishing units) to perform a fixed abrasive chemical-mechanical polishing of a wafer. This resolves the issue of having a decreasing polishing efficiency resulting from a gradual lowering of surface roughness in a polish layer. Hence, the time for completing a global planarization is reduced and the possibility of having residual material on the surface is minimized.
Furthermore, because this invention uses the roughened surface of a polishing pad (the polishing units) to carry out a fixed abrasive chemical-mechanical polishing operation, thickness of the polishing layer no longer constitutes a restriction. This invention also removes the width restriction in a shallow trench isolation (STI) gap-fill process.
In addition, this invention also utilizes a wafer holder with a retainer ring having a groove pattern to execute a fixed abrasive chemical-mechanical wafer polishing operation. Through the groove pattern on the retainer ring, the polishing pad (the polishing units) is re-conditioned in-situ to maintain a rough surface. Therefore, the upper surface of the polishing pad is able to maintain a roughened surface despite the gradual reduction in the roughness level of the polished wafer.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In this invention, silicon oxide is used as the dielectric material in the following illustration. However, the fixed abrasive chemical-mechanical polishing method can be applied to other types of material as well.
As shown in
However, as the silicon oxide layer 212 is gradually planarized, roughness on the surface of the silicon oxide layer 212 is also reduced. Since the capacity to remove adhesive compound 210 from the polishing pad 204 will drop after a while, the polishing rate will drop. Therefore, in the following, another polishing step is carried out using a second polishing pad with a roughened surface.
As shown in
As shown in
The polishing pad 304 comprises a plurality of abrasive units 311. The abrasive units 311 are shaped into a triangular cone, hexagonal cone or circular cylinder and set up as an array. Each abrasive unit 311 comprises a layer of adhesive compound 210 with a plurality of evenly distributed abrasive particles 208 therein. The adhesive compound 210 is an adhesive resin, for example. Aside from the abrasive units 311, the polishing pad 302 also has a polishing platen (not shown) underneath. The platen is fabricated from a material including, aluminum alloy or stainless steel. Note that if the layer to be polished is a silicon oxide, cerium oxide (CeO2) abrasive particles 208 are preferably used because it has a higher polishing selectivity relative to the silicon oxide.
As shown in
As shown in
This invention utilizes the roughened surface of a polishing pad (the polishing units) to perform a fixed abrasive chemical-mechanical polishing of a wafer. This resolves the issue of having a decreasing polishing efficiency due to a gradual lowering of the roughness of a polish surface. Hence, the time for completing a global planarization is reduced and the possibility of having residual material on the polish surface is minimized.
Furthermore, because this invention uses the roughened surface of a polishing pad (the polishing units) to carry out a fixed abrasive chemical-mechanical polishing operation, thickness of the polishing layer no longer constitutes a restriction. This invention also removes the width restriction in a shallow trench isolation (STI) gap-fill process.
In addition, this invention also utilizes a wafer holder with a retainer ring having a groove pattern to execute a fixed abrasive chemical-mechanical wafer polishing operation. Through the groove pattern on the retainer ring, the polishing pad (the polishing units) is re-conditioned in-situ to maintain a rough surface. Therefore, the upper surface of the polishing pad is able to maintain a roughened surface despite the gradual reduction in the roughness level of the polished wafer.
If cerium oxide (CeO2) is used as the abrasive particles in this invention, an optimal polishing selectivity between silicon oxide and silicon nitride is produced. Consequently, residual silicon oxide on a silicon nitride layer can be removed.
Finally, the polishing pad in this invention is fabricated using a plurality of abrasive units each comprising some adhesive compound enclosing a plurality of abrasive particles. However, the polishing pad may be fabricated as a single adhesive compound layer that encloses a plurality of evenly distributed abrasive particles.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A polishing pad, comprising:
- a plurality of abrasive units each containing: an adhesive compound; and a plurality of abrasive particles distributed evenly within the adhesive compound, wherein the surface of the abrasive units in contact with the surface of a wafer is roughened and the abrasive units are shaped into a triangular cone, hexagonal cone or circular cylinder and set up as an array.
2. The polishing pad of claim 1, wherein material constituting the abrasive particles comprises cerium oxide (CeO2).
3. The polishing pad of claim 1, wherein material constituting the adhesive compound comprises a resin.
4. A method of polishing a wafer, comprising the steps of:
- providing a first polishing pad, wherein the first polishing pad comprises a plurality of first abrasive units each fabricated using an adhesive compound with evenly distributed abrasive particles therein;
- performing a first polishing operation on the first polishing pad to planarize a wafer;
- providing a second polishing pad, wherein the second polishing pad comprises a plurality of second abrasive units each fabricated using an adhesive compound with evenly distributed abrasive particles therein, and the surface of the second abrasive units in contact with the wafer is roughened and the abrasive units are shaped into a triangular cone, hexagonal cone or circular cylinder and set up as an array; and
- performing a second polishing operation on the second polishing pad.
5. The wafer polishing method of claim 4, wherein material constituting the abrasive particles comprises cerium oxide (CeO2).
6. The wafer polishing method of claim 4, wherein material constituting the adhesive compound comprises a resin.
7-10. (cancelled)
11. The wafer polishing method of claim 4, wherein the second polishing operation is conducted at a rate faster than that of the first polishing operation.
12. The wafer polishing method of claim 4, wherein the second polishing operation is conducted at least at a same rate as the first polishing operation.
Type: Application
Filed: Sep 4, 2003
Publication Date: Mar 10, 2005
Inventors: Teng-Chun Tsai (Hsinchu), Hsiao-Ling Lu (Jhudong Township), Shin-Ku Chu (Hsinchu Hsien), Gene Li (Jhubei City)
Application Number: 10/655,806