Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: An intra-area connection order determining unit determines at random orders of connection of scan path circuits in each area divided by an placement area dividing unit. An inter-area connection order determining unit determines orders of connection of the scan path circuits between the areas such that length of interconnection between the areas divided by the placement area dividing unit becomes short. Accordingly, length of interconnection between the scan paths can be locally made short, reducing congestion of interconnections and generation of hold time errors.

Abstract: A datapath extraction unit extracts, from among datapaths on which a timing verification is to be performed, those datapaths from a netlist, timing constraints, and a cell library, that are established between at least two child blocks of a parent block. A datapath output unit prepares and presents to a user a datapath list in which timing exceptions can be specified. A timing constraint modification unit modifies the previous timing constraints according to the timing exceptions specified by the user and creates new timing constraints.

Abstract: An automatic placement and routing apparatus includes an initial power supply setting section for setting initial power supply potentials of cells; a placement and routing section for performing placement, global routing and detail routing of the cells according to a netlist and timing constraint information; a timing verification section for performing the timing verification of the specified paths according to the layout information at a particular stage of the placement and routing; and a power supply modification section for changing, when a cell having a timing problem is detected, the power supply potential of the cell. When the cell having a timing problem is detected, the placement and routing section optimizes the layout according to the change of the power supply potential of the cell, and the timing verification section performs the timing verification of the specified paths according to the layout information optimized.

Abstract: A method employed to determine a wire arrangement includes the steps of: arranging cells; performing a general routing; using maximum and minimum values of resistance, capacitance and other values stored in a library to calculate maximum and minimum delay times, the resistance, capacitance and other values being previously calculated through a simulation performed as a process parameter and a determinant of geometry as seen in plane are varied; if maximum delay and minimum delay times fall within a tolerable timing range, then performing a specific routing.

Abstract: A timing information generating apparatus includes an input/output information identifying unit, a delay time calculating unit and a timing information output unit. The input/output information identifying unit compares logical connection information with a library to identify intra-block input stage sequential circuits contributing to information exchange with extra-block input stage sequential circuits, and intra-block output stage sequential circuits contributing to information exchange with extra-block output stage sequential circuits. According to timing constraint information, the delay time calculating unit sets first delay times from input pins to the intra-block input stage sequential circuits, and second delay times from the intra-block output stage sequential circuits to output pins. The timing information output unit outputs timing information including the first delay times and the second delay times.

Abstract: A datapath extraction unit extracts, from among datapaths on which a timing verification is to be performed, those datapaths from a netlist, timing constraints, and a cell library, that are established between at least two child blocks of a parent block. A datapath output unit prepares and presents to the user a datapath list in which timing exceptions can be specified. A timing constraints modification unit modifies the previous timing constraints according to the timing exceptions specified by the user and creates new timing constraints.

Abstract: A category classification unit determines a net of interest from nets that show information on the connection between cells defined in logical netlist information, searches the net of interest and the nets adjacent the net of interest in layout information, and classifies the net of interest and the adjacent nets into categories set while attention is paid to how potentials of the adjacent nets operate relatively to the potential of the net of interest defined in a constraint, based on the logical netlist information and logical information in a library. A parasitic element extraction unit extracts parasitic elements of extraction elements defined in the constraint for each of the categories into which the nets are classified by the category classification unit, and outputs connection information including the parasitic elements.

Abstract: Distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion is added to each of the portions (step ST2). Each time a cell forming a specific region of a logic circuit is laid out, a layout of the logic circuit in that region is analyzed, a logic optimization is executed to rewrite the net list of the logic circuit in that region so as not to alter the number of ports located on the boundary of the logic layer by using the distinguishing information, and the layout of the logic circuit in that region is modified on the basis of the rewritten net list (step ST3).

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: An intra-area connection order determining unit determines at random orders of connection of scan path circuits in each area divided by an placement area dividing unit. An inter-area connection order determining unit determines orders of connection of the scan path circuits between the areas such that length of interconnection between the areas divided by the placement area dividing unit becomes short. Accordingly, length of interconnection between the scan paths can be locally made short, reducing congestion of interconnections and generation of hold time errors.

Abstract: A category classification unit determines a net of interest from nets that show information on the connection between cells defined in logical netlist information, searches the net of interest and the nets adjacent the net of interest in layout information, and classifies the net of interest and the adjacent nets into categories set while attention is paid to how potentials of the adjacent nets operate relatively to the potential of the net of interest defined in a constraint, based on the logical netlist information and logical information in a library. A parasitic element extraction unit extracts parasitic elements of extraction elements defined in the constraint for each of the categories into which the nets are classified by the category classification unit, and outputs connection information including the parasitic elements.

Abstract: There is provided a semiconductor process determining method comprising: Step ST1 of inputting an input parameter from a input part; Step ST2 of obtaining the delay time of a certain circuit by means of simulation on a gate level by letting the output parameter of each wiring layer be a variable; Step ST3 of judging whether or not the simulation is completed; Step ST4 of extracting the output parameter of each wiring layer giving the shortest delay time; and Step ST5 of outputting the extracted output parameter of each wiring layer in a display part.

Abstract: An automatic placement and routing apparatus includes an initial power supply setting section for setting initial power supply potentials of cells; a placement and routing section for performing placement, global routing and detail routing of the cells according to a netlist and timing constraint information; a timing verification section for performing the timing verification of the specified paths according to the layout information at a particular stage of the placement and routing; and a power supply modification section for changing, when a cell having a timing problem is detected, the power supply potential of the cell. When the cell having a timing problem is detected, the placement and routing section optimizes the layout according to the change of the power supply potential of the cell, and the timing verification section performs the timing verification of the specified paths according to the layout information optimized.

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: An engineering-change method of a semiconductor circuit includes a P&R (placement and routing) step of conducting placement and routing and logical optimization using a first netlist to generate a second netlist and a first layout; an ECO (engineering-change order) step of making logical changes in design of the first netlist to generate a third netlist; an ECO-formal verification step of generating a fourth netlist by changing the second netlist such that the fourth netlist becomes logically equivalent to the third netlist; and another ECO step of generating a second layout by changing the first layout such that it matches the fourth netlist. This method can implement an engineering-change method of a semiconductor circuit capable of reducing the design period with eliminating design feedback to the logical optimization at the P&R step.

Abstract: A reference degree of wire congestion relating to the arrangement of fill-metal (or dummy wire) is pre-set, a degree of wire congestion in each of wiring areas of a semiconductor circuit is calculated, the degree of wire congestion in each wiring area is compared with the reference degree of wire congestion, and it is judged that fill-metal is arranged in a specific wiring area of a low wire congestion. To consider an adverse influence of fill-metal arranged in the specific wiring area in the design of a layout of the semiconductor circuit, an insertion amount of the fill-metal is set according to a wire existence probability of the specific wiring area and a target wire existence probability pre-set, and a circuit layout of the specific wiring area is assumed on condition that the fill-metal having the insertion amount is arranged in the specific wiring area.

Abstract: A macroblock is treated as a single unit when creating a layout for a semiconductor integrated circuit. The macroblock comprises at least a cell for implementing one or more functions which the macroblock has to perform, and a plurality of through path forming cells each used for forming a through path passing through the macroblock, the plurality of through path forming cells being inserted into the macroblock in advance of creating a layout for a semiconductor integrated circuit so that they are spread over the macroblock in a predetermined way. Preferably, each of the plurality of through path forming cells is a buffer.

Abstract: Distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion is added to each of the portions (step ST2). Each time a cell forming a specific region of a logic circuit is laid out, a layout of the logic circuit in that region is analyzed, a logic optimization is executed to rewrite the net list of the logic circuit in that region so as not to alter the number of ports located on the boundary of the logic layer by using the distinguishing information, and the layout of the logic circuit in that region is modified on the basis of the rewritten net list (step ST3).