Abstract: An automatic placement and routing method checks on a wiring density by scanning a measurement area defined on a routing layout pattern. If the wiring density exceeds an upper limit value, it automatically generates a layout pattern whose wiring density is less than an upper limit value by automatically carrying out one of the following steps: increasing wiring spacing; inserting a wiring inhibited region between wires; replacing a wire by a plurality of divided narrower wires; and forming part of the wiring on a different layer through contact holes. This makes it possible to solve problems of a conventional method in that narrowing a wire whose wiring density exceeds the upper limit value results in reducing reliability cause of an increase of the wire resistance and of the possibility of a break, and in that the design takes a lot of time because the replacement of the wiring requires much manpower.

Abstract: A logical net list of cells and nets through which the cells are connected with each other is prepared. The cells are composed of a timing-free cell, in which an input timing of a signal is not considered, and a plurality of timing-considered cells in which an input timing of a signal is considered. Also, dummy pin information is prepared to specify the timing-free cell because the design of a layout pattern of the timing-free cell is not desired. The correspondence of the dummy pin information to the logical net list is established to isolate the timing-free cell from the timing-considered cells by placing dummy pins on both sides of the timing-free cell.

Abstract: There is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step which comprises the steps of, based on design information completed to a placement step, determining a wiring route considering a shape of a via and/or the number of the via, estimating the number of routing tracks to be used in each search of the global routing step, and verifying the estimated result, thereby obtaining a layout according to a wiring estimate at the global routing step.

Abstract: An automatic placement and routing device comprises a standard-net connection regulator for regulating the connecting relations between standard nets and cells into a net list, a cell placement means for arranging the placement of cells on the basis of the connecting relations of the standard nets, and a variable-net connection regulator for regulating the connecting relations between variable nets and cells whose placement has already been completed by the cell placement means. Since, by this configuration, the connecting relations of the standard nets are regulated before the placement of cells, and the connecting relations of the variable nets are regulated after the placement of cells on the basis of the result of the placement, such effects as that the particular wiring is made short, and that the complexity of wiring is made small and so on can be obtained.

Abstract: An image zoomed-in area, in which an image planned to be zoomed in is displayed, is specified, shape data of a zoomed-in image area is calculated according to shape data of the image zoomed-in area, an arranging position of the zoomed-in image area in an image screen is determined, a remained area, which is obtained by removing the zoomed-in image area from the whole area of the image screen, is recognized, the image of the image zoomed-in area is zoomed in to display the zoomed-in image in the zoomed-in image area, and no image is displayed in the remained area. Therefore, the displaying processing for images of the remained area, for which no user carefully pay attention, can be omitted, and the image display of the zoomed-in image can be performed at high speed when the image zooming-in processing is performed to obtain the zoomed-in image.

Abstract: There is provided a semiconductor process determining method comprising: Step ST1 of inputting an input parameter from a input part; Step ST2 of obtaining the delay time of a certain circuit by means of simulation on a gate level by letting the output parameter of each wiring layer be a variable; Step ST3 of judging whether or not the simulation is completed; Step ST4 of extracting the output parameter of each wiring layer giving the shortest delay time; and Step ST5 of outputting the extracted output parameter of each wiring layer in a display part.

Abstract: A cell selecting and connecting unit selects a type of cell adapted to drive a shield wire with a logical value corresponding to a logical value of at least one of inputs to a cell that drives a target wire that requires shielding. The cell selecting and connecting unit connects a cell of a selected type to the cell that drives the target wire so that an additional cell placing unit places the cell of the selected type. A shield generating unit generates a shielding wire connected to the placed cell along the target wire.

Abstract: A shield circuit includes shielding wires and a shielding wire driving circuit, the shielding wires being provided along a target wire that requires shielding, and the shielding wire driving circuit driving the shielding wires with a logical value corresponding to a logical value of at least one of inputs to a cell that drives the target wire.

Abstract: An engineering-change method of a semiconductor circuit includes a P&R (placement and routing) step of conducting placement and routing and logical optimization using a first netlist to generate a second netlist and a first layout; an ECO (engineering-change order) step of making logical changes in design of the first netlist to generate a third netlist; an ECO-formal verification step of generating a fourth netlist by changing the second netlist such that the fourth netlist becomes logically equivalent to the third netlist; and another ECO step of generating a second layout by changing the first layout such that it matches the fourth netlist. This method can implement an engineering-change method of a semiconductor circuit capable of reducing the design period with eliminating design feedback to the logical optimization at the P&R step.

Abstract: A method of executing a benchmark test according to the present invention comprises: a benchmark test proceeding step in which at least one standard input data preinstalled in a computer is fed to a plurality of tools which are also preinstalled in a computer so as to execute a benchmark test for these tools, a benchmark test result storing step in which a plurality of benchmark test results obtained during the benchmark test proceeding step are stored, and a benchmark test result outputting step in which at least one test result is outputted on a test operator's request from the plurality of benchmark test results stored during the test result storing step. Due to this construction, benchmark test operators do not have to prepare individually an input data and a plurality of test tools for themselves, making it possible thereby to reduce the total cost for performing the benchmark test as a whole.

Abstract: A function cell capable of shortening the term necessary for circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell are obtained. The semiconductor device includes first and second function cells that realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection on the first function cell plane is almost the same as the position of the plane.

Abstract: A cell selecting and connecting unit selects a type of cell adapted to drive a shielding wire with a logical value corresponding to a logical value of at least one of inputs to a cell that drives a target wire that requires shielding. The cell selecting and connecting unit connects a cell of a selected type to the cell that drives the target wire so that an additional cell placing unit places the cell of the selected type. A shield generating unit generates a shielding wire connected to the placed cell along the target wire.

Abstract: A reference degree of wire congestion relating to the arrangement of fill-metal (or dummy wire) is pre-set, a degree of wire congestion in each of wiring areas of a semiconductor circuit is calculated, the degree of wire congestion in each wiring area is compared with the reference degree of wire congestion, and it is judged that fill-metal is arranged in a specific wiring area of a low wire congestion. To consider an adverse influence of fill-metal arranged in the specific wiring area in the design of a layout of the semiconductor circuit, an insertion amount of the fill-metal is set according to a wire existence probability of the specific wiring area and a target wire existence probability pre-set, and a circuit layout of the specific wiring area is assumed on condition that the fill-metal having the insertion amount is arranged in the specific wiring area.

Abstract: Layout of a semiconductor integrated circuit is designed based on predetermined designing rules. Vias are detected based on information about the layout designed. It is determined if there exists a close via. A close via is a via surrounded by vias on four sides. It is determined if there exists an equal potential via. An equal potential via is a via having a potential equal to the potential of said close via in the vias that surround said close via on four sides. If an equal potential via is detected, then the layout of the semiconductor integrated circuit is corrected by deleting the close via.

Abstract: A shield circuit includes shielding wires and a shielding wire driving circuit, the shielding wires being provided along a target wire that requires shielding, and the shielding wire driving circuit driving the shielding wires with a logical value corresponding to a logical value of at least one of inputs to a cell that drives the target wire.

Abstract: There is provided an automatic placement and routing device which automatically performs placement and routing upon cells constituting a logic circuit while optimizing a bus structure. Bus structure construction means (12) constructs the bus structure which is a structure of signal lines for making connection between the cells to provide a bus construction result, based on bus information held in a bus information holding portion (7), cell placement information, constraint information from a constraint information holding portion (9) and logic circuit information from a logic circuit information holding portion (8), when the logic circuit information held in the logic circuit information holding portion (8) does not completely specify the bus structure.