Patents by Inventor Genta Mizuno

Genta Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159167
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu Yu UEDA
  • Patent number: 10861869
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 8, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ryo Nakamura, Yu Ueda, Tatsuya Hinoue, Shigehisa Inoue, Genta Mizuno, Masanori Tsutsumi
  • Publication number: 20200105595
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR, Senaka Krishna KANAKAMEDALA, Fumitaka AMANO, Genta MIZUNO
  • Patent number: 10608010
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yujin Terasawa, Genta Mizuno, Yusuke Mukae, Yoshinobu Tanaka, Shiori Kataoka, Ryosuke Itou, Kensuke Yamaguchi, Naoki Takeguchi
  • Publication number: 20200020715
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: January 16, 2020
    Inventors: Ryo NAKAMURA, Yu UEDA, Tatsuya HINOUE, Shigehisa INOUE, Genta MIZUNO, Masanori TSUTSUMI
  • Patent number: 10529620
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Publication number: 20190280001
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Application
    Filed: June 7, 2018
    Publication date: September 12, 2019
    Inventors: Yujin TERASAWA, Genta MIZUNO, Yusuke MUKAE, Yoshinobu TANAKA, Shiori KATAOKA, Ryosuke ITOU, Kensuke YAMAGUCHI, Naoki TAKEGUCHI
  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya
  • Patent number: 10128261
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
  • Publication number: 20180090373
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Publication number: 20180019256
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Application
    Filed: October 24, 2016
    Publication date: January 18, 2018
    Inventors: Fumitaka AMANO, Takashi ARAI, Genta MIZUNO, Shigehisa INOUE, Naoki TAKEGUCHI, Takashi HAMAYA
  • Publication number: 20170287925
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 5, 2017
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Patent number: 9666594
    Abstract: A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: May 30, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Genta Mizuno, Masanori Tsutsumi, Jayavel Pachamuthu
  • Patent number: 9401309
    Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: July 26, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
  • Publication number: 20160071876
    Abstract: A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.
    Type: Application
    Filed: May 26, 2015
    Publication date: March 10, 2016
    Inventors: Genta MIZUNO, Masanori TSUTSUMI, Jayavel PACHAMUTHU
  • Publication number: 20160064281
    Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
  • Patent number: 9159739
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi
  • Publication number: 20150179662
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 25, 2015
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Publication number: 20140353738
    Abstract: A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
    Type: Application
    Filed: August 20, 2014
    Publication date: December 4, 2014
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi