Patents by Inventor Georg Seidemann

Georg Seidemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11177220
    Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Andreas Wolter, Bernd Waidhas, Thomas Wagner
  • Patent number: 11145577
    Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Sonja Koller, Georg Seidemann, Reinhard Mahnkopf, Bernd Waidhas
  • Patent number: 11134573
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Patent number: 11127813
    Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Andreas Augustin
  • Publication number: 20210273342
    Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
  • Patent number: 11107763
    Abstract: A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Thomas Wagner, Andreas Wolter, Georg Seidemann
  • Patent number: 11081541
    Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Sciriha, Georg Seidemann
  • Publication number: 20210193594
    Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Stephan STOECKL, Wolfgang MOLZER, Georg SEIDEMANN, Bernd WAIDHAS
  • Patent number: 11031699
    Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
  • Patent number: 11018114
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 10854590
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Richard Patten, Georg Seidemann, Christian Geissler
  • Publication number: 20200352035
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 5, 2020
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Patent number: 10816742
    Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
  • Publication number: 20200328182
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Bernd WAIDHAS, Georg SEIDEMANN, Andreas WOLTER, Thomas WAGNER, Stephan Stoeckl, Laurent MILLOU
  • Publication number: 20200312781
    Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Gianni SIGNORINI, Georg SEIDEMANN, Bernd WAIDHAS
  • Publication number: 20200286982
    Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: Veronica Sciriha, Georg Seidemann
  • Publication number: 20200273832
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
  • Patent number: 10727197
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Wolter, Thomas Wagner, Stephan Stoeckl, Laurent Millou
  • Publication number: 20200227388
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Patent number: 10714455
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber