Patents by Inventor George Bajor
George Bajor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6812108Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.Type: GrantFiled: March 19, 2003Date of Patent: November 2, 2004Assignee: Intersil CorporationInventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George Bajor
-
Publication number: 20030157778Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.Type: ApplicationFiled: March 19, 2003Publication date: August 21, 2003Applicant: Intersil CorporationInventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George Bajor
-
Patent number: 6551897Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.Type: GrantFiled: November 16, 2001Date of Patent: April 22, 2003Assignee: Intersil Americas Inc.Inventors: Patrick Anthony Begley, Donald Frank Hemmenway, George Bajor, Anthony Lee Rivoli, Jeanne Marie McNamara, Michael Sean Carmody, Dustin Alexander Woodbury
-
Patent number: 6441447Abstract: A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.Type: GrantFiled: August 11, 1999Date of Patent: August 27, 2002Assignee: Intersil CorporationInventors: Joseph A. Czagas, George Bajor, Leonel Enriquez, Chris A. McCarty
-
Publication number: 20020076915Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.Type: ApplicationFiled: November 16, 2001Publication date: June 20, 2002Applicant: HARRIS CORPORATIONInventors: Patrick Anthony Begley, Donald Frank Hemmenway, George Bajor, Anthony Lee Rivoli, Jeanne Marie McNamara, Michael Sean Carmody, Dustin Alexander Woodbury
-
Patent number: 6365953Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.Type: GrantFiled: April 1, 1999Date of Patent: April 2, 2002Assignee: Intersil Americas Inc.Inventors: Patrick Anthony Begley, Donald Frank Hemmenway, George Bajor, Anthony Lee Rivoli, Jeanne Marie McNamara, Michael Sean Carmody, Dustin Alexander Woodbury
-
Publication number: 20010045614Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.Type: ApplicationFiled: April 1, 1999Publication date: November 29, 2001Inventors: PATRICK ANTHONY BEGLEY, DONALD FRANK HEMMENWAY, GEORGE BAJOR, ANTHONY LEE RIVOLI, JEANNE MARIE MCNAMARA, MICHAEL SEAN CARMODY, DUSTIN ALEXANDER WOODBURY
-
Patent number: 5976944Abstract: FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.Type: GrantFiled: February 12, 1997Date of Patent: November 2, 1999Assignee: Harris CorporationInventors: Joseph Andre Czagas, George Bajor, Leonel Ernesto Enriquez
-
Patent number: 5933746Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.Type: GrantFiled: April 23, 1996Date of Patent: August 3, 1999Assignee: Harris CorporationInventors: Patrick Anthony Begley, Donald Frank Hemmenway, George Bajor, Anthony Lee Rivoli, Jeanne Marie McNamara, Michael Sean Carmody, Dustin Alexander Woodbury
-
Patent number: 5892264Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.Type: GrantFiled: January 21, 1997Date of Patent: April 6, 1999Assignee: Harris CorporationInventors: Christopher K. Davis, George Bajor, James D. Beasom, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli
-
Patent number: 5807780Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.Type: GrantFiled: June 5, 1995Date of Patent: September 15, 1998Assignee: Harris CorporationInventors: Christopher K. Davis, George Bajor, James D. Beasom, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli
-
Patent number: 5744852Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.Type: GrantFiled: September 19, 1996Date of Patent: April 28, 1998Assignee: Harris CorporationInventors: Jack H. Linn, George Bajor, George V. Rouse
-
Patent number: 5668397Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.Type: GrantFiled: October 4, 1993Date of Patent: September 16, 1997Assignee: Harris Corp.Inventors: Christopher K. Davis, George Bajor, James D. Beasom, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli
-
Patent number: 5633180Abstract: A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy.Type: GrantFiled: June 1, 1995Date of Patent: May 27, 1997Assignee: Harris CorporationInventor: George Bajor
-
Patent number: 5603779Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.Type: GrantFiled: May 17, 1995Date of Patent: February 18, 1997Assignee: Harris CorporationInventors: Jack H. Linn, George Bajor, George V. Rouse
-
Patent number: 5504033Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.Type: GrantFiled: November 15, 1994Date of Patent: April 2, 1996Assignee: Harris CorporationInventors: George Bajor, Anthony L. Rivoli
-
Patent number: 5395774Abstract: Methods of forming a carbon containing, minority carrier barrier layer on the surface of a semiconductor, which methods may be used to form barriers between the emitter of a single crystal transistor and a polysilicon layer in electrical contact therewith, and thus transistors with an emitter with enhanced efficiency.Type: GrantFiled: September 7, 1993Date of Patent: March 7, 1995Assignee: Harris CorporationInventors: George Bajor, Anthony L. Rivoli, Jack H. Linn
-
Patent number: 5382541Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird 's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.Type: GrantFiled: August 26, 1992Date of Patent: January 17, 1995Assignee: Harris CorporationInventors: George Bajor, Anthony L. Rivoli
-
Patent number: 4900689Abstract: A process includes selectively forming laterally adjacent complementary doped epitaxial layers over low resistive buried regions of a horizontally isolated substrate. Self-aligned oxide mask are used for the epitaxial deposition. Lateral dielectric isolation trenches at the complementary doped epitaxial boundary complete the isolation of the islands. Base and emitter regions are formed in the epitaxial collector layers.Type: GrantFiled: December 8, 1988Date of Patent: February 13, 1990Assignee: Harris CorporationInventors: George Bajor, Hugh C. Nicolay
-
Patent number: 4897362Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.Type: GrantFiled: September 2, 1987Date of Patent: January 30, 1990Assignee: Harris CorporationInventors: Jose A. Delgado, George Bajor