Patents by Inventor George D. Papasouliotis
George D. Papasouliotis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7863190Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.Type: GrantFiled: November 20, 2009Date of Patent: January 4, 2011Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Mihai Buretea, Collin Mui
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Patent number: 7863194Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.Type: GrantFiled: April 14, 2010Date of Patent: January 4, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Heyun Yin, George D. Papasouliotis, Vikram Singh
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Publication number: 20100273322Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.Type: ApplicationFiled: April 22, 2010Publication date: October 28, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin
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Publication number: 20100240201Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.Type: ApplicationFiled: April 14, 2010Publication date: September 23, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE,INC.Inventors: Heyun YIN, George D. Papasouliotis, Vikram Singh
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Patent number: 7790633Abstract: A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired dielectric film thickness is achieved.Type: GrantFiled: September 11, 2006Date of Patent: September 7, 2010Assignee: Novellus Systems, Inc.Inventors: Raihan M. Tarafdar, George D. Papasouliotis, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie
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Patent number: 7737013Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.Type: GrantFiled: October 21, 2008Date of Patent: June 15, 2010Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Heyun Yin, George D. Papasouliotis, Vikram Singh
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Patent number: 7687787Abstract: A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.Type: GrantFiled: November 7, 2008Date of Patent: March 30, 2010Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, George D. Papasouliotis, Ziwei Fang, Richard Appel, Vincent Deno, Vikram Singh, Harold M. Persing
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Publication number: 20100022076Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
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Publication number: 20090324849Abstract: Several embodiments of a method for sealing pores on a porous substrate are disclosed. In one embodiment, the method comprises introducing first particles to the surface of the substrate and damaging the surface to decrease the size of the pores on the surface; introducing second particle to the surface; and forming a film on the surface covering the pores, where the film has a dielectric constant of 4 or less.Type: ApplicationFiled: December 28, 2008Publication date: December 31, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPEMENT ASSOCIATES, INC.Inventors: George D. PAPASOULIOTIS, Vikram Singh
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Patent number: 7625820Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.Type: GrantFiled: June 21, 2006Date of Patent: December 1, 2009Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Mihai Buretea, Collin Mui
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Publication number: 20090278059Abstract: A method and apparatus are described herein which allow the progression of delamination of a film to be monitored. An interferometer is used to detect the onset and progression of thin film delamination. By projecting one or more wavelengths at a surface, and measuring the reflectance of these projected wavelengths, it is possible to monitor the progression of the delamination process. Testing has shown that different stages of the delamination process produce different reflectance graphs. This information can be used to establish implantation parameters, or can be used as an in situ monitor. The same techniques can be used for other applications. For example, in certain implantation systems, such as PECVD, a film of material may developed on the walls of the chamber. The techniques described herein can be used to monitor this separation, and determine when preventative maintenance may be performed on the chamber.Type: ApplicationFiled: April 23, 2009Publication date: November 12, 2009Inventors: Helen Maynard, George D. Papasouliotis
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Patent number: 7589028Abstract: Methods of forming dielectric films with increased density and improved film properties are provided. The methods involve exposing dielectric films to microwave radiation. According to various embodiments, the methods may be used to remove hydroxyl bonds, increase film density, reduce or eliminate seams and voids, and optimize film properties such as dielectric constant, refractive index and stress for particular applications. In certain embodiments, the methods are used to form conformal films deposited by a technique such as PDL. The methods may be used in applications requiring low thermal budgets.Type: GrantFiled: November 15, 2005Date of Patent: September 15, 2009Assignee: Novellus Systems, Inc.Inventors: Seon-Mee Cho, Mike Barnes, Michelle Schulberg, George D. Papasouliotis
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Publication number: 20090227096Abstract: A method of forming a retrograde material profile in a substrate includes forming a surface peak profile on the substrate. Ions are then implanted into the substrate to form a retrograde profile from the surface peak profile, at least one of an ion implantation dose and an ion implantation energy of the implanted ions being chosen so that the retrograde profile has a peak concentration that is positioned at a desired distance from the surface of the substrate.Type: ApplicationFiled: March 7, 2008Publication date: September 10, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, George D. Papasouliotis
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Publication number: 20090200461Abstract: A method of controlling a plasma doping process using a time-of-flight ion detector includes generating a plasma comprising dopant ions in a plasma chamber proximate to a platen supporting a substrate. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. A spectrum of ions present in the plasma is measured as a function of ion mass with a time-of-flight ion detector. The total number ions impacting the substrate is measured with a Faraday dosimetry system. An implant profile is determined from the measured spectrum of ions. An integrated dose is determined from the measured total number of ions and the calculated implant profile. At least one plasma doping parameter is modified in response to the calculated integrated dose.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Deven M. Raj, Ludovic Godet, Bernard Lindsay, Timothy Miller, George D. Papasouliotis
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Publication number: 20090117735Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.Type: ApplicationFiled: October 21, 2008Publication date: May 7, 2009Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Heyun YIN, George D. Papasouliotis, Vikram Singh
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Publication number: 20090084987Abstract: A plasma processing apparatus includes a process chamber, a source configured to generate a plasma in the process chamber, and a platen configured to support a workpiece in the process chamber. The platen is biased with a pulsed platen signal having pulse ON and OFF time periods to accelerate ions from the plasma towards the workpiece during the pulse ON time periods and not the pulse OFF time periods. A plate is positioned in the process chamber. The plate is biased with a plate signal to accelerate ions from the plasma towards the plate to cause an emission of secondary electrons from the plate during at least a portion of one of the pulse OFF time periods of the pulsed platen signal to at least partially neutralize charge accumulation on the workpiece.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic GODET, Svetlana RADOVANOV, George D. PAPASOULIOTIS, Deven M. RAJ, Vikram SINGH, Timothy J. MILLER, Ziwei FANG
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Publication number: 20090061605Abstract: A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.Type: ApplicationFiled: November 7, 2008Publication date: March 5, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic GODET, George D. Papasouliotis, Ziwei Fang, Richard Appel, Vincent Deno, Vikram Singh, Harold M. Persing
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Patent number: 7491653Abstract: A metal- and metalloid-free nanolaminate dielectric film can be formed according to a pulsed layer deposition (PDL) process. A metal- and metalloid-free compound is used to catalyze the reaction of silica deposition by surface reaction of alkoxysilanols. Films can be grown at rates faster than 30 nm per exposure cycle. The invention can be used for the deposition of both doped (e.g., PSG) and undoped silicon oxide films. The films deposited are conformal, hence the method can accomplish void free gap-fill in high aspect ratio gaps encountered in advanced technology nodes (e.g., the 45 nm technology node and beyond), and can be used in other applications requiring conformal dielectric deposition.Type: GrantFiled: December 23, 2005Date of Patent: February 17, 2009Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Seon-Mee Cho, Ron Rulkens, Mihai Buretea, Dennis M. Hausmann, Michael Barnes
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Patent number: 7482247Abstract: Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.Type: GrantFiled: September 19, 2006Date of Patent: January 27, 2009Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Raihan M. Tarafdar, Ron Rulkins, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie, Wai-Fan Yau, Brian G. Lu, Timothy M. Archer, Sasson Roger Somekh
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Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition
Patent number: 7297608Abstract: A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500° C. in an oxidizing environment. The method includes the following three principal operations: exposing a substrate surface to an aluminum-containing precursor gas to form a substantially saturated layer of aluminum-containing precursor on the substrate surface; exposing the substrate surface to a silicon-containing precursor gas to form the dielectric film; and annealing the dielectric film in a low temperature oxygen-containing high density plasma. The resulting film has improved mechanical properties, including minimized seams, improved WERR, and low intrinsic stress, comparable to a high temperature annealing process (˜800° C.), but without exceeding the thermal budget limitations of advanced devices.Type: GrantFiled: June 22, 2004Date of Patent: November 20, 2007Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Raihan M. Tarafdar, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie