Patents by Inventor George E. Bailey

George E. Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100225067
    Abstract: A ring seal includes an annular body having a first side surface, a second side surface opposite the first side surface, a top surface, and a bottom surface opposite the top surface. A coating of silica particles is disposed on at least one of the first side surface, the second side surface, the top surface, and the bottom surface of the annular body. The coating of silica particles includes a composition comprising diatomaceous earth.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 9, 2010
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventor: GEORGE E. BAILEY
  • Patent number: 7298458
    Abstract: Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: November 20, 2007
    Assignee: LSI Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 7098996
    Abstract: Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: August 29, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 7023530
    Abstract: A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 4, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 7005217
    Abstract: A photolithographic mask for receiving light at a wavelength, phase, and intensity and printing a desired image on a substrate with an optical system. The mask is formed on an optically transmissive substrate, called a mask blank. The mask blank is preferably one hundred percent transmissive of the light intensity at the wavelength. At least one layer of an attenuated material that is at least partially transmissive to the wavelength of the light is formed on the optically transmissive substrate. The at least one layer of the attenuated material preferably blocks from about fifty percent to about ninety-four percent of the intensity of the light at the wavelength, whereas the prior art masks use materials that block about six percent of the intensity of the light at the wavelength. The attenuated material defines three feature types on the mask, including a primary image having edges, a scattering bar disposed near the edges of the primary image, and a background region.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: George E. Bailey, Neal P. Callan, John V. Jensen
  • Patent number: 6943055
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6894762
    Abstract: A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: May 17, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 6885436
    Abstract: Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: April 26, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Publication number: 20040197674
    Abstract: A photolithographic mask for receiving light at a wavelength, phase, and intensity and printing a desired image on a substrate with an optical system. The mask is formed on an optically transmissive substrate, called a mask blank. The mask blank is preferably one hundred percent transmissive of the light intensity at the wavelength. At least one layer of an attenuated material that is at least partially transmissive to the wavelength of the light is formed on the optically transmissive substrate. The at least one layer of the attenuated material preferably blocks from about fifty percent to about ninety-four percent of the intensity of the light at the wavelength, whereas the prior art masks use materials that block about six percent of the intensity of the light at the wavelength. The attenuated material defines three feature types on the mask, including a primary image having edges, a scattering bar disposed near the edges of the primary image, and a background region.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 7, 2004
    Inventors: George E. Bailey, Neal P. Callan, John V. Jensen
  • Patent number: 6764749
    Abstract: A method to improve the resolution of a photolithography system by using one or more coupling layers between a photo resist and an anti-reflective coating. The coupling layer(s) compensate for a mis-match in indexes of reflection between the photo resist and anti-reflective coating and minimize the amount of energy which is reflected back into the photo resist, thereby improving the quality of the resulting image which is formed on the photo resist during the process.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: July 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey
  • Publication number: 20040069407
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Application
    Filed: July 28, 2003
    Publication date: April 15, 2004
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Publication number: 20040067421
    Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Inventors: Michael J. Berman, George E. Bailey
  • Publication number: 20040018448
    Abstract: A method to improve the resolution of a photolithography system by using one or more coupling layers between a photo resist and an anti-reflective coating. The coupling layer(s) compensate for a mis-match in indexes of reflection between the photo resist and anti-reflective coating and minimize the amount of energy which is reflected back into the photo resist, thereby improving the quality of the resulting image which is formed on the photo resist during the process.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 29, 2004
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 6627466
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6102143
    Abstract: A cutting element is composed of a metal carbide stud having an outer hemispherical distal end which has a series of annular ridges. The tops of the annual ridges are substantially non-planar, i.e., curvilinear, such that the angle formed between the slope on either side is less than 120.degree.. There are no surfaces tangent to vertical on such ridges. A layer of polycrystalline superabrasive material is disposed over the annular ridges. This cutter is easily manufacturable as the metal stud can be pressed and extracted from the punch without further machining and the surface geometry of the metal stud allows for complete PCD compaction during diamond sintering.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 15, 2000
    Assignee: General Electric Company
    Inventors: Shelly R. Snyder, George E. Bailey, Eoin O'Tighearnaigh