Patents by Inventor George E. Pax

George E. Pax has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111707
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 4, 2024
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Patent number: 11855048
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 26, 2023
    Inventors: Thomas H. Kinsley, George E. Pax
  • Patent number: 11789890
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Patent number: 11721742
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Publication number: 20230084286
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Patent number: 11589480
    Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards
  • Publication number: 20230048780
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Inventors: Thomas H. Kinsley, George E. Pax
  • Patent number: 11508422
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Patent number: 11488938
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax
  • Publication number: 20220335000
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 20, 2022
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Patent number: 11416437
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Publication number: 20220071061
    Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Thomas H. Kinsley, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards
  • Patent number: 11206749
    Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. For example, a memory module may have a printed circuit board (PCB) having an edge connector, a plurality of memory devices disposed on a surface of the PCB, and a tubular heat spreader disposed along an edge of the PCB opposite the edge connector. The tubular heat spreader may comprise a tubular portion open at both ends thereof to permit the through flow of a cooling gas; and two planar elements extending in parallel away from the tubular portion and configured to provide a friction fit with the memory module. Each of the planar elements may be configured to convey thermal energy from the memory module to the tubular portion.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards
  • Publication number: 20210367057
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Patent number: 11081565
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Publication number: 20210217737
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Application
    Filed: March 31, 2021
    Publication date: July 15, 2021
    Inventors: Thomas H. Kinsley, George E. Pax
  • Publication number: 20210144840
    Abstract: A heat spreader configured for use with a dual-in line memory module (DIMM) is provided. The heat spreader comprises a thermally conductive body having upper and lower edges with a first length, opposing side edges with a second length less than the first length, and a planar surface configured for attachment to a plurality of co-planar semiconductor devices of the DIMM, and a retaining clip configured to releasably attach the thermally conductive body to the DIMM when disposed within a side notch of the DIMM and around a first one of the opposing side edges of the thermally conductive body.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventor: George E. Pax
  • Patent number: 10978426
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax
  • Publication number: 20210035617
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Publication number: 20210036125
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards