Patents by Inventor George J. Korsh
George J. Korsh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7972909Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: GrantFiled: April 17, 2009Date of Patent: July 5, 2011Assignee: Intel CorporationInventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Patent number: 7968976Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: GrantFiled: March 18, 2010Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John M. Nugent, Ed Nabighian
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Publication number: 20100187528Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: ApplicationFiled: March 18, 2010Publication date: July 29, 2010Inventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Publication number: 20090200548Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: ApplicationFiled: April 17, 2009Publication date: August 13, 2009Inventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Patent number: 7566915Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: GrantFiled: December 29, 2006Date of Patent: July 28, 2009Assignee: Intel CorporationInventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Publication number: 20080157284Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Patent number: 7035151Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: GrantFiled: June 14, 2004Date of Patent: April 25, 2006Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Patent number: 6992937Abstract: A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.Type: GrantFiled: July 28, 2003Date of Patent: January 31, 2006Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, William John Saiki, George J. Korsh
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Publication number: 20040233716Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: ApplicationFiled: June 14, 2004Publication date: November 25, 2004Applicant: Agate Semiconductor, Inc.Inventors: Hieu van Tran, Sakhawat M. Khan, George J. Korsh
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Patent number: 6751118Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: GrantFiled: August 13, 2001Date of Patent: June 15, 2004Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Patent number: 6590825Abstract: A non-volatile flash fuse element and an array of such elements include fuses coupled to the input of a latch arranged as a differential comparator for constant current differential sensing. The fuse element includes a margining circuit that provides differential mass fuse margining. The margining circuit also allows the fuses to be stressed and screened. The fuse elements also provide constant current parallel programming.Type: GrantFiled: November 1, 2001Date of Patent: July 8, 2003Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, William John Saiki, George J. Korsh, Sakhawat M. Khan
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Publication number: 20030086326Abstract: A non-volatile flash fuse element and an array of such elements include fuses coupled to the input of a latch arranged as a differential comparator for constant current differential sensing. The fuse element includes a margining circuit that provides differential mass fuse margining. The margining circuit also allows the fuses to be stressed and screened. The fuse elements also provide constant current parallel programming.Type: ApplicationFiled: November 1, 2001Publication date: May 8, 2003Inventors: Hieu Van Tran, William John Saiki, Sakhawat M. Khan, George J. Korsh
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Patent number: 6519180Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: GrantFiled: August 13, 2001Date of Patent: February 11, 2003Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Patent number: 6504754Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: GrantFiled: July 2, 2001Date of Patent: January 7, 2003Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Patent number: 6487116Abstract: An integrated circuit memory system and method for precision hot carrier injection programming of single or plurality of nonvolatile memory cells is described. Each program cycle is followed by a verify cycle. Precision programming is achieved by incrementally changing a programming current pulse flowing between the source and drain in the memory cell during successive program cycles and a constant current during successive verify cycles. Current control and voltage mode sensing circuitry reduces circuit complexity, reduces programming cell current, lowers power dissipation, and enables page mode operation. Precision programming is useful for multilevel digital and analog information storage.Type: GrantFiled: July 20, 2001Date of Patent: November 26, 2002Assignee: Silicon Storage Technology, Inc.Inventors: Sakhawat M. Khan, George J. Korsh
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Patent number: 6396742Abstract: In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.Type: GrantFiled: July 28, 2000Date of Patent: May 28, 2002Assignee: Silicon Storage Technology, Inc.Inventors: George J. Korsh, Sakhawat M. Khan, Hieu Van Tran
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Publication number: 20020041516Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: ApplicationFiled: August 13, 2001Publication date: April 11, 2002Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Publication number: 20020039322Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: ApplicationFiled: August 13, 2001Publication date: April 4, 2002Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Publication number: 20020036920Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.Type: ApplicationFiled: July 2, 2001Publication date: March 28, 2002Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
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Publication number: 20010050863Abstract: An integrated circuit memory system and method for precision hot carrier injection programming of single or plurality of nonvolatile memory cells is described. Each program cycle is followed by a verify cycle. Precision programming is achieved by incrementally changing a programming current pulse flowing between the source and drain in the memory cell during successive program cycles and a constant current during successive verify cycles. Current control and voltage mode sensing circuitry reduces circuit complexity, reduces programming cell current, lowers power dissipation, and enables page mode operation. Precision programming is useful for multilevel digital and analog information storage.Type: ApplicationFiled: July 20, 2001Publication date: December 13, 2001Inventors: Sakhawat M. Khan, George J. Korsh