Abstract: Disclosed is an integrated circuit device or chip which digitally synthesizes human speech using a linear predictive filter. This device may be implemented using conventional processing techniques. For instance, when implemented in conventional P-channel MOS technology, the disclosed device or chip has an active area of approximately 45,000 square mils.

Abstract: Disclosed is a parameter interpolator for a speech synthesis circuit. Using a parameter interpolator permits the data rate to the speech synthesis circuit to be lowered inasmuch as the incoming speech data is used to slowly charge the data previously inputted to the values of the incoming data. The speech synthesis circuit includes an input circuit for receiving the target values of the speech data and a memory for stored interpolated values of the speech data. The interpolator includes a circuit coupled to the input circuit and the memory which calculates the difference between the target values and the stored values. Another circuit is used to add a portion of the difference to the values stored in the memory; the particular portion of the difference is equal to 1/2N where N=0, 1, 2 . . . Further, the interpolator is arranged to inhibit the normal interpolation upon certain conditions, such as changes from voiced speech to unvoiced speech, and visa versa.

Abstract: A circuit and method for actuating a display, especially a liquid crystal display, and a keyboard using a common set of conductors. The circuit includes circuits for generating appropriate display potentials, scanning pulses and sensing the scanning pulses. Certain of the display potentials applied to the display device are also applied to the keyboard. Certain of these potentials applied to the keyboard also have a scanning pulse superimposed thereon. Circuits for sensing the scanning pulses are associated with the circuits which generate the other potentials applied to the keyboard; these other potentials preferably float during the generation of the scanning pulses.By using the disclosed circuit, a calculator chip for actuating a multi-character position liquid crystal display and for scanning a keyboard may be packaged in a conventional twenty-eight pin package. By appropriately controlling the circuit, a keyboard can be scanned with negligible effect on the liquid crystal display device.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator which permits direct or indirect addressing while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip is embodied in the present invention. All memory instructions contain an address select bit to choose either the address contained in the ROM instruction word or the contents of the RAM address register which is loaded from the adder output. The RAM address register contents are incremented or added to by the adder to provide indirect addressing of the RAM while the ROM instruction word provides direct addressing of the RAM.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. The segment and digit drivers which are fabricated on the same semiconductor chip utilizing I.sup.2 L techniques have grounded emitters requiring a relatively large power drain to produce blank segments. A unique feature of the calculator is an automatic blanking circuit which turns off both the segment and digit drivers for blank digits to provide no power drain while selectively enabling the digit drivers and segment drivers so that the keyboard can be scanned utilizing the same digit drivers.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a dual adder which selectively functions as a multibit word adder and also as a plurality of single bit adders. This dual functioning adder cooperates with the calculator system in such a manner as to reduce the total amount of circuitry required to implement the calculator function thereby permitting fabrication on the smaller chip. The dual adder is utilized, for example, to perform bit operations for use in flagging and 2's complement addition for subtraction operations as well as normal multibit word addition.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a latched decoder for multiplexed digit outputs to the display. The latched decoder reduces the circuitry ordinarily utilized to provide the digit outputs to permit fabrication on the smaller chip. The digit outputs are selected one or more at a time by a load output instruction. A selected number of bits of the load output instruction selects the digit.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip. The condition latch state is determined, for example, by the logical OR of up to four flags after a test flag instruction, by the logical OR of up to four keyboard inputs after a test key instruction, by the carry output of the adder after any add instruction, or by the results of an adder compare after any compare instruction.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator which permits direct instruction compares while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip is embodied in the present invention. The adder and adder input circuits allow a direct comparison of the contents of an addressed RAM word and the contents of the accumulator, a constant and the contents of the accumulator, or a constant and the contents of the RAM address register.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator which provides power-up clear to reset the calculator to a "zero" idle state when the calculator power is initially turned on is smaller and more reliable than the conventional open loop power-up clear circuits which rely entirely on an RC time constant thereby permitting fabrication on the smaller chip. The power-up clear circuit is a latch which forces the input of the program counter shift register to an initial logical state. The latch is reset by the logical NAND of the program counter outputs.