Abstract: SOI islands having doped edges are formed by providing over the surface of a layer of single crystalline silicon on an insulating substrate a masking layer formed of two layers, the lowermost layer adjacent the silicon layer being silicon oxide and the uppermost layer being silicon nitride. The masking layer is defined using standard photolithographic techniques and etching to form the masking layer over only the areas of the silicon layer which are to form the islands. The uncovered portion of the silicon layer is then removed by etching to form the islands. The lowermost layer of the masking layer is then etched laterally away from the edges of the island to expose a portion of the surface of the silicon layer adjacent the edges of the islands. After removing the uppermost layer of the masking layer, the exposed edge portions of the surface of the silicon layer are doped by ion implantation to form the islands with doped edges.

Abstract: A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. A means is provided within the insulating substrate for minimizing the collection of radiation-induced charge carriers at the interface between the layer of semiconductor material and the insulating substrate. This means significantly reduces the accumulation of positive charges in the insulating substrate which would otherwise cause back-channel leakage when the device is operated after being irradiated. Also, the means minimizes the collection of charge carriers injected from the insulating substrate into the semiconductor device disposed on the insulating substrate. A method of fabricating this semiconductor device is also disclosed.

Abstract: An SOS integrated circuit includes a plurality of spaced islands of single-crystalline silicon on a surface of a sapphire substrate. A conformal layer of silicon oxide is on the surface of the sapphire substrate between the islands and extends along a portion of the side surfaces of the islands. A layer of polycrystalline silicon is over the silicon oxide layer and extends over the side surface and at least a portion of the top surface of the islands. A separate field-effect transistor is on each island and includes source and drain regions spaced by a channel region and a channel dielectric layer over the channel region. The polycrystalline silicon layer may extend over the channel dielectric to serve as the gate of the transistor. The method of making the circuit includes depositing the silicon oxide layer over the sapphire substrate surface and the islands, and applying a layer of a negative photoresist over the silicon oxide layer.

Abstract: An additive that absorbs light at a given wavelength is added to a solder flux composition for use in laser soldering wherein the laser emits light of said given wavelength. The additive reduces the power required to melt the solder-flux combination and thereby improves soldering efficiency.

Abstract: Indicia are formed in a sapphire substrate by ion implantation with a sufficient amount of silicon ions to establish a contrast with the remainder of the substrate. The implant is annealed at 1050.degree. to 1200.degree. C. under an oxygen or inert atmosphere. The implants are stable to repeated heatings to elevated temperature. The implants are further beneficial in that they do not introduce a source of contamination into the substrate.

Abstract: The semiconductor device includes a layer of silicon nitride (Si.sub.3 N.sub.4) beneath a phosphosilicate glass (PSG) layer. A silicon nitride impervious layer prevents the oxidation of underlying, exposed silicon regions during a "flow" step and any "reflow" step. Accordingly, the flow of the PSG layer can be conducted in an atmosphere containing steam, which means that the PSG layer can contain less than about 7% phosphorus by weight. The reduction of the phosphorus content of the PSG layer provides increased reliability for the semiconductor device. The method of manufacturing such a device is also disclosed.

Abstract: A process of forming a low-dose ion implant of one or more of phosphorus, arsenic or boron is described. The desired impurity ion implant is preceded by an amorphizing implant of at least about 10.sup.15 ions/cm.sup.2 of fluorine ions. The implants are advantageously annealed at a temperature below about 800.degree. C.

Abstract: Multilevel metallization structures in semiconductor devices are improved by utilizing a two- or three-layer dielectric system wherein the dielectric layers differ in flow temperature by at least 50.degree. and preferably 100.degree. C., so that one layer may be flowed without reflow or mutual dissolution with an underlying contacting dielectric layer. The first dielectric layer is phosphosilicate glass and the second is borophosphosilicate glass. A third layer is also borophosphosilicate glass differing in composition from the second so as to provide the required flow temperature differential.

Abstract: The contact resistance between a layer of conductive material, such as a metal or conductive polycrystalline silicon, and either a body of single crystalline silicon or another layer of the conductive material is reduced by implanting ions of a neutral material through the conductive layer into either the silicon body or the other conductive layer. After the implantation of the neutral ions, the device is annealed.

Abstract: In making a semiconductor device wherein a film of a non-single crystalline silicon, such as polycrystalline or amorphous silicon, is deposited on a substrate and then doped, particularly by ion implantation, to make the film conductive, the conductivity of the film is increased by pre-annealing the film at a temperature of 1000.degree. C. to 1200.degree. C. in an inert ambient before doping the film.

Abstract: The invention is a method for diffusing phosphorus into the surface of a silicon substrate using borophosphosilicate glass as the phosphorus source.

Abstract: A selective chemical etchant solution for phosphosilicate glass includes a carboxylic acid, hydrogen fluoride and water. The invention is also a method for preferentially etching the phosphosilicate glass which comprises the step of immersing the glasses in the etchant solution of the invention.

Abstract: A process for defining improved tapered contact openings in glass coatings comprising the deposition of a layer of low temperature flowable passivating glass and the deposition of a masking layer to initially approximately define contact areas over portions of the active regions and over portions of a gate line. The first contact openings are then etched and the passivating layer caused to reflow followed by a second etch, in the previously etched areas, which second etch accurately defines the contact openings. The final etch rounds off any corners produced by the second etch to produce smoothly tapered contact openings. .circle.

Abstract: A method of detecting a cathodic corrosion site on a metallized substrate comprises depositing molecules of a pH sensitive fluorescent dye adjacent a metallic surface of the substrate, the metallic surface having a corrosion site thereon characterized by a reduction of the hydronium ion to hydrogen (2H.sup.+ +2e.sup.- .fwdarw.H.sub.2). An electrical bias is then applied across the metallic surface, and the fluorescent dye is exposed to ultraviolet (UV) radiation, whereby fluorescence is activated at the cathodic corrosion site.

Abstract: The semiconductor device includes a layer of silicon nitride (Si.sub.3 N.sub.4) beneath a phosphosilicate glass (PSG) layer. A silicon nitride impervious layer prevents the oxidation of underlying, exposed silicon regions during a "flow" step and any "reflow" step. Accordingly, the flow of the PSG layer can be conducted in an atmosphere containing steam, which means that the PSG layer can contain less than about 7% phosphorus by weight. The reduction of the phosphorus content of the PSG layer provides increased reliability for the semiconductor device. The method of manufacturing such a device is also disclosed.

Abstract: An etching solution for etching composite structures of silicon nitride on silicon oxide on silicon substrates which etches the silicon nitride at a rate equal to or faster than the silicon oxide which comprises concentrated aqueous hydrogen fluoride in a high boiling, organic solvent.

Abstract: A method of rounding a sharp semiconductor projection jutting out from a principal body of semiconductor material comprises the step of irradiating the projection with a laser pulse having an energy density of less than about 1.5 joules/cm.sup.2.

Abstract: A method of inspecting electrical devices such as integrated circuit devices which have conductors covered by a protective layer of passivating material to determine the quality of the protective layer includes treating the circuit with a fluorescein containing dye and exposing the treated device to UV radiation while applying a voltage between two conductors. Fluorescence is observable in well passivated areas of the device but not in unpassivated or inadequately passivated areas. When a device is tested before dicing from a wafer, adjacent devices to which no voltage is applied fluoresce in both passivated and unpassivated areas.

Abstract: The semiconductor device includes a layer of silicon nitride (Si.sub.3 N.sub.4) beneath a phosphosilicate glass (PSG) layer. A silicon nitride impervious layer prevents the oxidation of underlying, exposed silicon regions during a "flow" step and any "reflow" step. Accordingly, the flow of the PSG layer can be conducted in an atmosphere containing steam, which means that the PSG layer can contain less than about 7% phosphorus by weight. The reduction of the phosphorus content of the PSG layer provides increased reliability for the semiconductor device. The method of manufacturing such a device is also disclosed.

Abstract: The formation of thin-film resistors by the ion implantation of a metallic conductive layer in the surface of a layer of phosphosilicate glass or borophosphosilicate glass which is deposited on a silicon substrate. The metallic conductive layer materials comprise one of the group consisting of tantalum, ruthenium, rhodium, platinum and chromium silicide. The resistor is formed and annealed prior to deposition of metal, e.g. aluminum, on the substrate.