Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.

Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.

Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.

Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.

Abstract: A first clock stage in a circuit utilizes a second stage clock for triggering the falling edge of a first clock stage output. The output will not reset until both the first clock is low and the second clock are high due to the addition of the second clock signal. This is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal. The clock signal is inverted by an inverter connected to the gate of the additional P-FET. Stability is provided to the first stage by creating a full keeper, which holds the output from the logic device in the first stage. A pair of transistors are connected by their drains to the output of the logic device. The transistors are controlled by an inverter, which is connected to the pairs' bases, wherein the inverter receives the output from the logic device.

Abstract: A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.

Abstract: A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.

Abstract: A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the storage array, setting a flag to inhibit access to the portion of the array accessed by the failing entity and storing and retrieving data from remaining portions of the array. The present invention is well adapted for use with n-way set associative cache storage arrays.

Abstract: A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.