Abstract: Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer. The invention forms a polish stop insulator (e.g., nitride) over the insulator layer in, for example, a liquid phase chemical vapor deposition (LPCVD) process. The polish stop insulator fills in the scratches. The invention then forms an opening through the insulator layer and through the polish stop insulator (e.g., in a reactive ion etching (RIE) process) and deposits a conductor within the opening. The invention performs a second CMP process on the conductor. The polish stop insulator is harder than the insulating layer and prevents the second CMP process from scratching the insulator layer. The invention removes portions of the polish stop insulator to leave the polish stop insulator only within the scratches.

Abstract: A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.

Abstract: A process of fabricating a field effect transistor (FET) device uses the simultaneous implantation of the well species at the edge of the device and at the bottom of the shallow trench isolation (STI). This not only simplifies the process by defining the region for implantation at the device edge and at the bottom of the isolation with a single photo masking level, it also avoids the dual problems of corner Vt degradation and leakage across the bottom of the isolation trench. By implantation of the well species into the corner of the device region, the degradation of the corner Vt is mitigated by the additional channel doping in the edge of the device. The leakage across the bottom of the STI is eliminated by the simultaneous implantation of the well species at the interface thus raising the dopant level of the parasitic channel.

Abstract: A system monitors usage of a tool in a tool set and warns an operator and/or prevents usage of a tool chosen by an operator, subject to possible override by the operator, if permitted, in order to balance usage among tools of the tool set and verify operational conditions of tools of the tool set through usage. The system and method are entirely transparent to the operator and the operator is permitted full flexibility of tool choice unless tool usage becomes unbalanced. The system and method preferably limits usage based on length of consecutive usage and percentage of product processed by each tool. Use of new, modified or repaired tools is also prevented until the tool is certified for a particular process and defined to the system.

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

Abstract: Disclosed is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout layer having an opening in correspondence with the portion of the would-be silicon mesa where a channel stop is desired is formed. N type dopant is introduced into the exposed silicon followed by an anneal step to and vertically diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region. Upon forming a pair of highly P doped regions on either side of the shallow highly N doped region, the latter functions as a channel stop to arrest charge leakage between the P doped regions due to parasitic FET action at the trench walls.

Abstract: A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed thereover and openings are formed therein by reactive ion etching to provide substantially horizontal surfaces and substantially vertical sidewalls. The vertical sidewalls of the openings are formed at the desired locations of the narrow dimensioned structures. A second, conformal insulating layer is then formed followed by a reactive ion etching step which substantially removes the horizontal portions of the second insulating layer. The remaining polycrystalline silicon layer is removed to leave a pattern of self-supporting narrow dimensioned dielectric regions on the major surface of the substrate. The narrow dimensioned dielectric regions can be used as a mask to form narrow structures in the substrate.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of as layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: Disclosed is a complementary vertical NPN and PNP pair having matched performance. The PNP collector is located deep in an epitaxial layer overlying a semiconductor substrate. The junction depths and surface concentrations of both emitters are quite similar; the junction depths and surface concentrations of bases of the complementary devices are also similar to each other. The PNP and NPN emitters are provided with self-aligned conductive contacts. A high dopant concentration equal to that in the emitters is provided in all contacts of the transistor elements to reduce the contact resistances.Disclosed too is a process of forming the above structure. Starting with a semiconductor substrate having a blanket N+ NPN subcollector and an epitaxial layer thereon having first and second active regions, an NPN base precursor and PNP collector reach-through precursor are simultaneously implanted in the first and second active regions, respectively.

Abstract: Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region in an N type monocrystalline silicon body and masking it with an insulator (e.g. dual oxide-nitride) layer, the highly doped N region (hereafter, N+ region) is formed in a portion of the P doped region by selectively opening the insulator layer and introducing N dopant therethrough. This opening also serves as contact opening for the N+ region. contact opening for the P region is formed by selectively etching the insulator layer. The structure is subjected to a low temperature steam oxidation to from an oxide layers in the P contact and N+ contact regions, the oxide in the N+ contact being about 3-5 times thicker than that in the P contact region due to the significantly higher oxidation rate of the N+ region relative to the P doped region.

Abstract: A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material which functions as the first capacitor plate, a doped polysilicon layer provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer interposed between the two plates serving as the capacitor's dielectric. Since the polysilicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

Abstract: An integrated bipolar transistor having a self-aligned polysilicon base contact is formed by depositing a first doped polysilicon layer and a silicon nitride passivating layer on the surface of a semiconductor substrate having an isolated collector region therein. An opening is formed in the first polysilicon and silicon nitride layers over the collector to expose the surface of the semiconductor substrate. The base region is formed through the opening and a conformal silicon nitride coating is then deposited on the wall of the opening and over the surface of the semiconductor substrate within the opening. A second polysilicon layer is formed on the silicon nitride passivating layer. The second polysilicon layer is reactive ion etched, leaving a polysilicon sidewall on the wall of the opening while removing the rest of the second polysilicon layer. The polysilicon sidewall is then oxidized, and an emitter is formed through the opening.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing approximate dopant materials into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate.

Abstract: A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.

Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: Deep trenches (14,15) are formed according to the desired pattern through the N epitaxial layer (13) and N.sup.+ subcollector region (12) into the P.sup.- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches, SiO.sub.2 and Si.sub.3 N.sub.4 layers (17,19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO.sub.2 /Si.sub.3 N.sub.4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud.

Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.