Abstract: A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.

Abstract: A method for forming adjacent impurity regions of differing conductivities in a semiconductor substrate without using lithography. N type impurities of a first conductivity are introduced into the substrate to form first impurity regions. The substrate is then oxidized to create a mask having a thickness which is greater over the N type impurity regions than over the remainder of the substrate. A portion of the masking layer is then removed, preferably by dip-etching, to a depth which is sufficient to re-expose the substrate only. Impurities of a second conductivity are then introduced in the substrate adjacent the N type impurity regions, with the remaining portion of the mask protecting the N type impurity regions from introduction of the second impurities therein.