Patents by Inventor George V. Rouse

George V. Rouse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7052973
    Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: May 30, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
  • Patent number: 6909146
    Abstract: A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: June 21, 2005
    Assignee: Intersil Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller
  • Patent number: 6825532
    Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: November 30, 2004
    Assignee: Intersil Americas Inc.
    Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
  • Patent number: 6812108
    Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: November 2, 2004
    Assignee: Intersil Corporation
    Inventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George Bajor
  • Patent number: 6798024
    Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: September 28, 2004
    Assignee: Intersil Americas Inc.
    Inventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George S. Bajor
  • Publication number: 20040180512
    Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
  • Publication number: 20030157778
    Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.
    Type: Application
    Filed: March 19, 2003
    Publication date: August 21, 2003
    Applicant: Intersil Corporation
    Inventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George Bajor
  • Publication number: 20020189640
    Abstract: Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1→AF/HCL→SC-2 wafer cleaning process has a metal concentration no greater than 1×109. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.
    Type: Application
    Filed: June 17, 1999
    Publication date: December 19, 2002
    Inventors: JACK H. LINN, GEORGE V. ROUSE, SANA RAFIE, ROBERTA R. NOLAN-LOBMEYER, DIANA LYNN HACKENBERG, STEVEN T. SLASOR, TIMOTHY A. VALADE
  • Patent number: 6455379
    Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: September 24, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
  • Publication number: 20010022379
    Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
    Type: Application
    Filed: March 6, 2001
    Publication date: September 20, 2001
    Applicant: Intersil Corporation
    Inventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
  • Publication number: 20010016399
    Abstract: In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.
    Type: Application
    Filed: May 1, 2001
    Publication date: August 23, 2001
    Applicant: HARRIS CORPORATION
    Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
  • Patent number: 6255195
    Abstract: In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: July 3, 2001
    Assignee: Intersil Corporation
    Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
  • Patent number: 6246090
    Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: June 12, 2001
    Assignee: Intersil Corporation
    Inventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
  • Patent number: 5932022
    Abstract: Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1.fwdarw.HF/HCL.fwdarw.SC-2 wafer cleaning process has a metal concentration no greater than 1.times.10.sup.9. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: August 3, 1999
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, George V. Rouse, Sana Rafie, Roberta R. Nolan-Lobmeyer, Diana Lynn Hackenberg, Steven T. Slasor, Timothy A. Valade
  • Patent number: 5849627
    Abstract: Low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: December 15, 1998
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller
  • Patent number: 5744852
    Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: April 28, 1998
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, George Bajor, George V. Rouse
  • Patent number: 5603779
    Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: February 18, 1997
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, George Bajor, George V. Rouse
  • Patent number: 5569620
    Abstract: Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon-nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: October 29, 1996
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller
  • Patent number: 5517047
    Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: May 14, 1996
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller, William H. Speece
  • Patent number: 5387555
    Abstract: Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers. The silicide bonding takes place in the presense of a liquid oxidizer such as aqueous solution of HNO.sub.3 and H.sub.2 O.sub.2.
    Type: Grant
    Filed: September 3, 1992
    Date of Patent: February 7, 1995
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller