Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Abstract: Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.

Abstract: An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices.

Abstract: An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during thread switching. Register overwrite buffers preserve thread resources in overlapping registers during the thread switching process. Thread resources are loaded into the corresponding register subsets or, when overlapping register subsets are employed, into either the corresponding register subset or the corresponding register overwrite buffer. A thread status register is utilized by a thread controller to keep track of READY/NOT-READY threads, the active thread, and whether single-thread or multithread operations are permitted. Furthermore, the registers in the register subsets include a thread identifier field to identify the corresponding thread.

Abstract: A system and method for progressively identifying and configuring the nodes of a network having an unknown or partially unknown topology are presented. A special all-node address indicator is designated for insertion in a packet to be sent from a given node with known node address to a next adjacent node with unknown node address. Each node contains a port control register for each port of the node which when set instructs the node to insert the all-node address indicator into a packet to be forwarded to a next adjacent node in the network with unknown node address. The port control registers are remotely selectively set by one or more managing nodes of the network. Race condition is avoided by provision of a set count register associated with an address node register and managing node address register within each node of the network.

Abstract: A system and method for receiving and validating user input for a computer resource entered into a computing system or network, and distinguishing valid and invalid portions of the user input. The invalid resource identifier, which ranges from a least specific portion to a most specific portion, is partitioned into a plurality of fields. At least one of the fields corresponding to the most specific portion of the invalid resource identifier is removed from the invalid resource identifier to create a modified resource identifier, wherein the modified resource identifier is used to attempt to access a higher level computer resource. The fields corresponding to the most specific portion of the resource identifier are removed until the modified resource identifier proves to be a valid resource identifier which can access a computer resource.

Abstract: A networked computer system and method of communicating classify request packets into multiple classes, with one class devoted to non-propagable requests that may be handled locally by destination nodes in the computer system. The multiple classes of requests are separately handled in the networked computer system such that an inability of a node to handle a request in another class does not hinder the ability of the node to process non-propagable requests, thereby avoiding deadlocks in the computer system.

Abstract: The invention is a method to mark hypertext links in an image map that have been traversed. The invention actually modifies the image map of the links by inserting a marker or changing the color associated with the coordinates of a particular image link on the image map. The history files of links that have been traversed are first checked to determine if the image has changed or is otherwise out of date. The image map or a copy of the image map is then modified and displayed.

Abstract: A method for reissuing a command initiated by a master device to a slave device, where the slave device fails to process the command within a predetermined interval. The slave stores the command, including a master identifier used to identify the master device that initiated the command, at the slave device. The slave device arbitrates for control of the command bus when it becomes available to process the command. Upon receiving control of the bus, the slave device drives the stored command, including the master identifier, onto the command bus. It appears to the system that the master device reissued the command.