Patents by Inventor Georgios Palaskas

Georgios Palaskas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160182262
    Abstract: Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Andreas Jörn Leistner, Georgios Palaskas
  • Publication number: 20160181234
    Abstract: Apparatus having structures implementing compact and symmetric multi-way transformer combiners are described herein. In an embodiment, each unit device cell of a plurality unit device cells may include two metal layers on top of the unit device cell coupled to a multi-way transformer combiner by one of the two metal layers such that the configuration of the unit device cells with the multi-way transformer combiner is symmetric. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Hongtao Xu, Georgios Palaskas
  • Publication number: 20160095060
    Abstract: The disclosure relates to a method, apparatus and system to provide an integrated HUB for communicating with wearable devices. The exemplary devices include an Offloading engine to communicate directly with the wearable devices at reduced power and with relaxed radio specification requirement. In one embodiment, the disclosure relates to a system having one or more antennas; a platform radio to communicate with the one or more antennas; a platform processor to communicate with the platform radio; and a first logic to combine incoming data from one or more wearable sensors, the first logic configured to fuse incoming data from the one or more wearable sensors and to determine whether to awaken the host platform.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Applicant: Intel Corporation
    Inventors: Parmoon Seddighrad, Ashoke Ravi, Georgios Palaskas, Per Hammarlund
  • Patent number: 9288841
    Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel IP Corporation
    Inventors: Hasnain Lakdawala, Ashoke Ravi, Ofir Degani, Bernd-Ulrich Klepser, Zdravko Boos, Georgios Palaskas, Stefano Pellerano, Paolo Madoglio
  • Publication number: 20150381337
    Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Paolo Madoglio, Georgios Palaskas, Stefano Pellerano, Ashoke Ravi, Kailash Chandrashekar
  • Patent number: 9209958
    Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Georgios Palaskas, Paolo Madoglio, Stefano Pellerano, Ashoke Ravi, Kailash Chandrashekar
  • Patent number: 9194911
    Abstract: A digital on-die-test engine (OTE) generates stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: November 24, 2015
    Assignee: iNTEL CORPORATION
    Inventors: Georgios Palaskas, Jorge Hermosillo, Marian K. Verhelst
  • Patent number: 9172338
    Abstract: Various embodiments include a power amplifier having power amplifier cells located in a die, conductive contacts overlying a surface of the die and coupled to the amplifier cells, and conductive lines overlying a surface of the die between the conductive contacts and coupled to the power amplifier cells. Additional apparatus are described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Hongtao Xu, Georgios Palaskas
  • Publication number: 20150181643
    Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Inventors: Hasnain Lakdawala, Ashoke Ravi, Ofir Degani, Bernd-Ulrich Klepser, Zdravko Boos, Georgios Palaskas, Stefano Pellerano, Paolo Madoglio
  • Publication number: 20150091384
    Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Paolo Madoglio, Georgios Palaskas, Bernd-Ulrich Klepser, Andreas Menkhoff, Zdravko Boos, Andreas Boehme, Michael Bruennert
  • Publication number: 20150078482
    Abstract: Various embodiments include a power amplifier having power amplifier cells located in a die, conductive contacts overlying a surface of the die and coupled to the amplifier cells, and conductive lines overlying a surface of the die between the conductive contacts and coupled to the power amplifier cells. Additional apparatus are described.
    Type: Application
    Filed: June 1, 2012
    Publication date: March 19, 2015
    Inventors: Hongtao Xu, Georgios Palaskas
  • Patent number: 8502598
    Abstract: A digitally configurable transformer that performs switched transformer combining is disclosed. The flexible transformer includes switches that are dynamically configurable to efficiently combine RF power from power amplifier cores to achieve different power levels. The disclosed transformer is efficient at a broad range of power levels, leading to high power output efficiency. The transformer may be part of any power amplifier design that uses the transformer for power combining.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Parmoon Seddighrad, Hongtao Xu, Georgios Palaskas
  • Publication number: 20130173203
    Abstract: A digital on-die-test engine (OTE) is disclosed to generate stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 4, 2013
    Inventors: GEORGIOS PALASKAS, Jorge Hermosillo, Marian K. Verhelst
  • Patent number: 8472896
    Abstract: A method, system, apparatus and article are described for optimizing transformer power combiners and for dynamically controlling power for outphasing power amplifiers. In some embodiments, for example, an apparatus may comprise one or more outphasing power amplifiers, one or more phase modulator modules coupled to and operative to dynamically control the one or more outphasing power amplifiers, and one or more power combiners coupled to and operative to combine outputs from the one or more outphasing power amplifiers, wherein the one or more power combiners comprise transformer power combiners arranged to combine outphasing signals using a primary inductor and differential signals using a secondary inductor. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Hongtao Xu, Georgios Palaskas, Ashoke Ravi
  • Publication number: 20130082772
    Abstract: A digitally configurable transformer that performs switched transformer combining is disclosed. The flexible transformer includes switches that are dynamically configurable to efficiently combine RF power from power amplifier cores to achieve different power levels. The disclosed transformer is efficient at a broad range of power levels, leading to high power output efficiency. The transformer may be part of any power amplifier design that uses the transformer for power combining.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Inventors: Parmoon Seddighrad, Hongtao Xu, Georgios Palaskas
  • Patent number: 8222966
    Abstract: A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Paolo Madoglio, Marian Verhelst, Georgios Palaskas
  • Publication number: 20120161831
    Abstract: An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Ashoke Ravi, Pin-En Su, Paolo Madoglio, Georgios Palaskas
  • Patent number: 8207770
    Abstract: An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Pin-En Su, Paolo Madoglio, Georgios Palaskas
  • Publication number: 20120062331
    Abstract: A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 15, 2012
    Inventors: Ashoke Ravi, Paolo Madoglio, Marian Verhelst, Georgios Palaskas
  • Patent number: 7856212
    Abstract: Embodiments of a millimeter-wave phase-locked loop with an injection-locked frequency divider (ILFD) are generally described herein. Other embodiments may be described and claimed. In some embodiments, the ILFD uses a quarter-wavelength transmission line. A method of calibrating an ILFD is also provided to allow the ILFD to operate at or near the center of its locking range for each of a plurality of VCO oscillating frequency bands.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: December 21, 2010
    Assignee: Intel Corporation
    Inventors: Stefano Pellerano, Rajarshi Mukhopadhyay, Georgios Palaskas