Abstract: A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (ISSG) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.

Abstract: A dielectric structure and a manufacturing method thereof and a memory structure are provided. The dielectric structure includes a dielectric layer and a plurality of crystalline grains disposed in the dielectric layer. The dielectric layer includes a first high-K dielectric material with a first dielectric constant. Each crystalline grain includes a second high-K dielectric material with a second dielectric constant greater than the first dielectric constant and greater than 20. Each crystalline grain has a crystal structure, so that each crystalline grain has a third dielectric constant greater than the second dielectric constant. Whole dielectric constant of the dielectric structure can be raised by performing an annealing process to form the crystalline grains in the dielectric layer, and the capacity of the memory structure for storing electric charges can be increased.

Abstract: In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece.

Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Abstract: A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam.

Abstract: A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam.

Abstract: In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece.

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between ?40° C. and ?120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.

Abstract: A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming an offset spacer on the sidewall of the gate structure; forming a cap layer to cover the substrate and the gate structure; performing an ion implantation process to implant carbon atoms into the cap layer; performing a first etching process to form a recess in the substrate adjacent to two sides of the gate structure; and forming an epitaxial layer in the recess.

Abstract: A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench.