Abstract: Performing storage writes in a mirrored virtual machine system by receiving a state of a primary virtual machine during execution of an application, wherein the primary virtual machine runs on a first physical machine and a secondary virtual machine runs on a second physical machine, wherein the state is captured by checkpointing, and the primary virtual machine is configured to write data to a first block and concurrently write the data to a write buffer on the secondary virtual machine. The method also includes storing a copy of data within a second block to a rollback buffer for the secondary virtual machine, in response to identifying a checkpoint in the application, merging the rollback buffer with the write buffer, in response to detecting a failover, writing a copy of the rollback buffer to the disk storage, and continuing execution on the secondary virtual machine from the last checkpoint.

Abstract: A processing apparatus supports execution of executable computer program code, wherein non-instruction data is read from and written to a first address space, while executable instructions are fetched from a second address space. Preferably, the processing apparatus supports execution of a modified or enhanced computer program. The programs and user interfaces in the first address space see only the unmodified first program in the first address space and cannot detect the modified or enhanced program in the second address space.

Abstract: This invention relates to a method and framework for invisible code rewriting. A method, system, and computer program for allowing modification of executable program code in a computer platform comprising: providing a virtual address space on the platform, said virtual space comprising a first and second address space; identifying a program into the first address space; identifying an enhancement to the program; copying the program into the second address space; modifying the program copy in the second address space to provide the enhancement; and configuring the platform to execute the program and executing the enhanced program in second address space.

Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.

Abstract: A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition manager allocates primary processing units to the logical partition from a primary shared processor pool, and the logical partition is activated. The secondary processing units are reserved for the logical partition from a secondary shared processor pool, and the logical partition can be relocated to the secondary shared processor pool in response to a condition such as a hardware failure. The logical partition can continue to process its workload with the fewer processor resources, and can be restored to the primary processing unit entitlement.

Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.

Abstract: A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

Abstract: A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

Abstract: A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition manager allocates primary processing units to the logical partition from a primary shared processor pool, and the logical partition is activated. The secondary processing units are reserved for the logical partition from a secondary shared processor pool, and the logical partition can be relocated to the secondary shared processor pool in response to a condition such as a hardware failure. The logical partition can continue to process its workload with the fewer processor resources, and can be restored to the primary processing unit entitlement.

Abstract: A method, system, and computer program product enhances resource/process availability by providing hardware based buffering of network packets during checkpointing in a virtualized environment. A High Availability Checkpoint (HAC) utility pre-configures a physical network adapter to buffer outgoing network packets from virtual machines that employ a checkpointing technology. In response to receiving an outgoing network packet from a virtual machine and determining that the virtual machine employs a pre-specified checkpointing technology, the physical network adapter buffers the outgoing network packet. In addition, a primary host performs/facilitates checkpoint operations (associated with the virtual machine) with a secondary host. When checkpoint operations are successfully completed, the HAC utility triggers the transmission of the buffered network packets from the network adapter to a network destination.

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags.

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache including a cache controller (122); and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit is adapted to create a log (200) in the memory prior to running the virtual machine in said first operating mode; the cache controller is adapted to transfer a modified cache line from the cache to the memory; and write only the memory address of the transferred modified cache line in the log; and the processor unit is further adapted to update a further image of the virtual machine in a different memory location, e.g. on another computer system, by retrieving the memory addresses stored in the log, retrieve the modified cache lines from the memory addresses and update the further image with said modifications.

Abstract: A computer-implemented method provides checkpoint high-available for an application in a virtualized environment with reduced network demands. An application executes on a primary host machine comprising a first virtual machine. A virtualization module receives a designation from the application of a portion of the memory of the first virtual machine as purgeable memory, wherein the purgeable memory can be reconstructed by the application when the purgeable memory is unavailable. Changes are tracked to a processor state and to a remaining portion that is not purgeable memory and the changes are periodically forwarded at checkpoints to a secondary host machine. In response to an occurrence of a failure condition on the first virtual machine, the secondary host machine is signaled to continue execution of the application by using the forwarded changes to the remaining portion of the memory and by reconstructing the purgeable memory.

Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.

Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.

Abstract: A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.

Abstract: A computer-implemented method, computer program product and data processing system provide checkpoint high-available for an application in a virtualized environment with reduced network demands. An application executes on a primary host machine comprising a first virtual machine. A virtualization module receives a designation from the application of a portion of the memory of the first virtual machine as purgeable memory, wherein the purgeable memory can be reconstructed by the application when the purgeable memory is unavailable. Changes are tracked to a processor state and to a remaining portion that is not purgeable memory and the changes are periodically forwarded at checkpoints to a secondary host machine. In response to an occurrence of a failure condition on the first virtual machine, the secondary host machine is signaled to continue execution of the application by using the forwarded changes to the remaining portion of the memory and by reconstructing the purgeable memory.

Abstract: A method, system, and computer program product enhances resource/process availability by providing hardware based buffering of network packets during checkpointing in a virtualized environment. A High Availability Checkpoint (HAC) utility pre-configures a physical network adapter to buffer outgoing network packets from virtual machines that employ a checkpointing technology. In response to receiving an outgoing network packet from a virtual machine and determining that the virtual machine employs a pre-specified checkpointing technology, the physical network adapter buffers the outgoing network packet. In addition, a primary host performs/facilitates checkpoint operations (associated with the virtual machine) with a secondary host. When checkpoint operations are successfully completed, the HAC utility triggers the transmission of the buffered network packets from the network adapter to a network destination.

Abstract: A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.

Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.